This is a register map for EOS 600D. Registers are sorted by memory address.
Registers have usually the same meaning among all cameras. See also:
- Register_Map/60D
- Register_Map/550D
- Register_Map/40D
- Register_Map/Brute_Force
- Register Map/Clean HDMI
Looks like even compact cameras with DIGIC II and III share the same commands :) [1]
It is the try to create a more or less clean map of the different hardware modules mapped into memory space along with some example data.
FlashIF[]
0xC0000000 FlashIF Base
+0x000 [32] Flash Write Protect Control
-------1 -------- -------- -------- Disable Write Protect "ROM1" (0xF8000000)
+0x004 [32] Flash Write Protect Control
-------1 -------- -------- -------- Disable Write Protect "BootROM" (0xF0000000)
+0x010 [32] Flash Write Protect Control Key
-------- -------- xxxxxxxx xxxxxxxx Disable Write Protect "BootROM" (0xF0000000)
xxxxxxxx xxxxxxxx -------- -------- Disable Write Protect "ROM1" (0xF8000000)
Write 0xD9C5 in those 16 bits to disable WP line.
Power Control[]
0xC0F01000 PowerControl (PWR_CTRL) Base +0x000 [32] NRES +0x004 [32] LCLK
ObInteg[]
0xC0F0A000 ObInteg Base
+0x004 [32] Pixel count (resolution used from PROP_CAM_MODEL + 0x30)
-------- -------- xxxxxxxx xxxxxxxx X Resolution - 1
xxxxxxxx xxxxxxxx -------- -------- Y Resolution - 1
+0x00C [32] Reset?
-------- -------- -------- -------1 Enable? Reset?
+0x010 [32] Unknown
-------- -------- -------- xxxxxxx- Unknown, never set?
-------- -------- -------0 -------- Unknown, never set?
-------- -------- ---1---- -------- Unknown, always set?
-------- xxxxxxxx -------- -------- Unknown, always set to 0x04?
-------1 -------- -------- -------- Unknown, always set?
+0x020 [32] Result 0a (used)
+0x024 [32] Result 0b (used)
+0x028 [32] Result 0c (used)
+0x02C [32] Result 0d (used)
+0x030 [32] Result 1a
+0x034 [32] Result 1b
+0x038 [32] Result 1c
+0x03C [32] Result 1d
+0x040 [32] Result 2a
+0x044 [32] Result 2b
+0x048 [32] Result 2c
+0x04C [32] Result 2d
+0x050 [32] Result 3a
+0x054 [32] Result 3b
+0x058 [32] Result 3c
+0x05C [32] Result 3d
+0x060 [32] Result 4a
+0x064 [32] Result 4b
+0x068 [32] Result 4c
+0x06C [32] Result 4d
+0x100 [32]
-------- -------- -------- -------1 Enable EDMAC data processing? (enabled before, disabled after processing)
+0x108 [32] window top position
-------- -------- xxxxxxxx xxxxxxxx horizontal position
xxxxxxxx xxxxxxxx -------- -------- vertical position
+0x10C [32] window bottom position
-------- -------- xxxxxxxx xxxxxxxx horizontal position
xxxxxxxx xxxxxxxx -------- -------- vertical position
+0x110 [32] Debayer Method
0x22227777, 0x77772222, 0x8888DDDD or 0xDDDD8888
+0x12C [32] Unknown
-------- -------- -------- ----xxxx Unknown, never set?
-------- -------- -------- ---x---- Unknown, set most of the time
LVDS[]
0xC0400000 LVDS Base +0x454 [32] Used during initialization +0x47C [32] Used during initialization +0x480 [32] Used during initialization (set to 0x0, 0x10, 0x11 in that order) +0x484 [32] Used during initialization (ORRed with 0x02)
Watchdog[]
Uses IRQ level 3
0xC0410000 Watchdog Base
+0x000 [32] Used during initialization
11------ -------- -------- -------- Set during init
-------- -------- ----xxxx -------- Set during init, values 0-4
-------- -------- -------- xxxx---- Set during init, values 0-6
-------- -------- -------- -------1 Set during init
+0x004 [32] Probably wdt-reset - set to 0xAA55 periodically
+0x008 [32] Flags
-------- -------- -------- -------x Set when WDT timed out
CFDMA[]
0xC0620000 CF Base #0 (40D = 0xC0700000)
0xC0630000 CF Base #1 (unused?)
+0x0000 [8] CIS data (always or just in special modes?)
...
+0x0FFF [9]
+0x2000 [8] PIO DATA
+0x2001 [8] Read: Error data, Write: Features
+0x2002 [8] Sector count
+0x2003 [8] Sector number
+0x2004 [8] Cylinder low byte
+0x2005 [8] Cylinder high byte
+0x2006 [8] Drive/Head
+0x2007 [8] Read: Status, Write: Command
+0x200E [8] Read: Alt Status, Write: Device control
+0x8000 [32] init: 0x0001
+0x8004 [32] init: 0x003B
+0x8008 [32] init: 0xFFFF
+0x800C [32] Data register to feed with data (usually 0x2000)
+0x8010 [32] unknown, set to 0x100. maybe sector size?
+0x8014 [32] unknown, set to PIO_W:0x1E, PIO_R:0x16, DMA:0x00, init 5D3: 0x12
+0x8024 [32] PIO: Command register to use, OR'ed with 0xA000
+0x8028 [32] PIO: set to 9
+0x8030 [32] PIO: set to 0xFF0001
+0x8034 [32] PIO: set to 0x07FF5800 or 0xFF070058 depending on command reg
+0x8038 [32] PIO: set to 0xFEFF0100 or 0xFFFE0001 depending on command reg
+0x8040 [32] Enable interrupt when flag changed? 0, 1, 0x2000000
+0x8044 [32] Interrupt reason, write with negated value upon interrupt
+0x8048 [32] set to 1, maybe transfer count?
+0x8080 [32] Sector count
+0x8088 [32] unknown, set to 0 for PIO, 1 for DMA, 1 on init
+0x8090 [32] unknown, related to access timing
+0x809C [32] unknown, related to access timing
+0x80A0 [32] unknown, related to access timing (init 5D3: 0x63D3F14)
+0x80A4 [32] unknown, related to access timing (init 5D3: 0x61D3F06)
+0x80B0 [32] init: 0x0000
+0x80C0 [32] init: 0x0000
+0x8500 [32] init: 0x0000
+0x8504 [32] unknown, related to access timing
+0x8508 [32] unknown, related to access timing
+0x850C [32] UDMA access timing
UDMA 0: 7D: 0x1213 5D3: 0x1001616
UDMA 1: 7D: 0x0C0C 5D3: 0x1000F0E
UDMA 2: 7D: 0x0909 5D3: 0x1000B0B
UDMA 3: 7D: 0x0607 5D3: 0x1000808
UDMA 4: 7D: 0x0404 5D3: 0x1000505
UDMA 5: 7D: 0x0203 5D3: 0x0000303
UDMA 6: 7D: 0x0202 5D3: 0x0000202
+0x8518 [32] init 5D3: 0x1817100E
+0x8528 [32] init 5D3: 0x00010000
0xC0530000 CFDMA Base
+0x0000 [32] HDMAC_CA: Buffer address with data to transfer
+0x0004 [32] HDMAC_LEN: Bytes to transfer (multiple of 512)
+0x0010 [32] set to 0x3D(write) or 0x39(read) or 0x00(disable)
+0x0014 [32] HDMAC_ST: set to 0, lowest 4 bits are written negated upon interrupt
+0x0018 [32] set to 0
SDCON[]
0xC0C10000 SDCON Base (600D) (40D - hw was not released with SD slot)
0xC0C20000 SDCON Base
0xC0C30000 SDCON Base (5D3)
0xC0C40000 SDCON Base
+0x000 [32] Set to 0x00 on init
+0x004 [32] Set to 0x01 on init
+0x008 [32] Set to 0x00 on init, 0x01/0xF1 before read/write, not used for status block. means: use DMA?
+0x00C [32] Set to 0x14/0x13/0x12/0x11/0x02 on command, after writing regs +0x024, +0x020 and +0x010
with 0x11, registers +0x028/+0x02C is ignored probably
0x13 Write transfer
0x14 Read transfer
+0x010 [32] Status
---------------- ---------------1 Transfer finished
---------------- --------------1- Error
-----------1---- ---------------- DAT transfer data available in reg +0x06C?
----------1----- ---------------- DAT transfer finished?
+0x014 [32] Set to 0x03 before transfer start, 0x00 on ISR
+0x018 [32] Set to 0x08 on init
+0x020 [32] Command frame lower 32 bits (needs 0x01 being set, end bit)
+0x024 [32] Command frame upper 16 bits (needs 0x4000 being set, transmission bit)
+0x028 [32] Written with 0x88/0x30/0x30 before CMD
+0x02C [32] Written with 0x7F08/0x2701/0x80000000 before CMD
+0x034 [32] Data received lower 32 bits
+0x038 [32] Data received upper 16 bits
+0x058 [32] SD bus width
-----------0---0 1 bit
-----------0---1 4 bit
-----------1---0 8 bit
+0x05C [32] Write transfer block size
+0x064 [32] SD bus width
----01100000---- -----------0---0 1 bit
----01100000---- -----------0---1 4 bit
----01110000---- -----------1---0 8 bit
+0x068 [32] Read transfer block size
+0x070 [32] Some busy flags, set to 0x39 before transfer
---------------1 Transfer running
+0x07C [32] Read/Write transfer block count
+0x080 [32] Transferred blocks
+0x084 [32] SDREP: Status register/error codes
+0x088 [32] SDBUFCTR: Set to 0x03 before reading
---------------1 Write transfer
--------------1- Read transfer
0xC0510000 SDDMA Base
+0x060 [32] Transfer memory address
+0x064 [32] Transfer byte count
+0x070 [32] Flags/Status, set to 0x39 before read transfer start, 0x29|0x04 before write
---------------1 Transfer finished
-------------1-- Write transfer
-----------1---- use 16 byte wide DMA transfers
+0x078 [32] Written with zero before transfer start. position?
JPCORE[]
The JPCore seems to an extra processor based engine that exists at three base addresses with equivalent layouts. JPCORE is e.g. used in YUV2JPEG while JP57 in RAW2JPEG. Those seem both to support lossless compression. It also handles MPEG compression, only seen in JP62 yet.
It uses its own firmware in main memory, the address (!) where it was copied into RAM is written to +0x928 before init. Its size is approx 16-18KiB, depending on its exact instance. The address must be aligned to 0x80 bytes.
There is also a buffer address written to 0x92C which is 0x5000 bytes big and starts with the 32 bit word 0x00500000 and the character sequence "xbuf". Seems not to be used in main firmware, perhaps it is the JPCORE's internal scratchpad memory? Seems the first word is indeed two 16 bit words.
0xC0E00000 JPCORE Base
0xC0E10000 JP62 Base
+0x000 [32] JP62_OPCR (Operation Configuration Register?)
-------- -------- -------1 -------- OPINPROG (Operation in Progress?)
-------1 -------- -------- -------- Startup Success
-------- -------- -------- ------1- Reset Engine after operation?
-------- -------- -------- -------1 Enable Engine?
+0x00C [32] JP62_OPMR (Operation Mode Register?)
00000000 00000000 10100000 10010000 H264 0-Frame
00000000 00000000 10100000 10000011 H264 0-Frame (H264_SPS_PPS)
00000000 00000000 10000000 10010000 H264 P-Frame
00000000 00000000 10000000 10010000 H264 I-Frame
+0x020 [32] JP62_ (read after interrupts. reason?)
+0x040 [32] JP62_ 0x600
+0x044 [32] JP62_INSTR (Interrupt Status Register)
-------- -------- ------1- -------- IEVSUS (Interrupt Vector Suspend?)
-------- -------- -----1-- -------- IEVCPLT
+0x080 [32] JP62_SIZER
-------- -------- xxxxxxxx xxxxxxxx (X Resolution >> 4) 16x16 Macroblocks?
xxxxxxxx xxxxxxxx -------- -------- (Y Resolution >> 4)
+0x0C0 [32] JP62_SEQCR1 (0x1280142)
+0x0D0 [32] JP62_PICCR1
-------- -------- -------- --xxxxxx QPY
-------- -------- --xxxxxx -------- QPC
-------- -------1 -------- -------- Set
+0x0E0 [32] JP62_SLCCR1
-------- -------- -------- -----101 0/P-Frame
-------- -------- -------- -----111 I-Frame
-------- --xxxxxx -------- -------- Slice QPD
+0x0E4 [32] JP62_SLCCR2
-------- -------- ----xxxx -------- Deblock Alpha
-------- -------- xxxx---- -------- Deblock Beta
+0x0FC [32] JP62_MISCR (0x200)
+0x928 [32] JpCoreFirm (written by InitializeJpCore2Driver)
+0x92C [32] JpCoreExtStream (written by InitializeJpCore2Driver)
0xC0E20000 JP57 Base (Lossless)
+0x000 Control/status register?
x------- -------- -------- -------- set when configuring; expected 0 in JPEGICError
-------- -------- -------- -------x set when starting operation
-------- -------x -------- -------- expected 1 before starting read edmacs (else, error code 0x8017)
-------x -------- -------- -------- expected 1 above (matches Startup Success?)
+0x004 Maybe mode?
0x0010002 = Encode
0x001000A = Decode
0x0010008 = ?
0x1010000 = ?
0x0000007 = During CaptureInit
+0x008 1
+0x010-0x01C JPEG tags in order of appearance, packed as LE 32 bit words
e.g. RAW preview L unknown
+0x010 0xDAC3C4D8 / 0xC4C0DBD8 / 0xDAC0DBD8
+0x014 0x000000D9 / 0x0000D9DA / 0x000000D9
+0x018 0x00000000 / 0x00000000 / 0x00000000
+0x024 output size - number of written bytes for write channel 1
+0x030 JPEGIC status?
-------- -------x xxxxxxxx xxxxxxxx all expected 1 in JPEGICError
+0x040 0x600
+0x044 matches JP62_INSTR?
+0x050 0
+0x080 JP57_SIZER (slice size in px; see also 0xE8 and 0xEC; http://lclevy.free.fr/cr2/#lossless )
-------- -------- xxxxxxxx xxxxxxxx X Resolution (slice width = image width / 2)
xxxxxxxx xxxxxxxx -------- -------- Y Resolution (slice height = image height)
+0x084 Sample properties? for SOF3 header?
---- xxxx ---- ---- Theory: Number of components
---- ---- ---- xxxx Theory: Sample precision
0x030F = MRAW/SRAW
0x0308 = unused code?
0x020E = RAW
+0x088
0x030201 = MRAW/SRAW
0x000201 = RAW
+0x08C Component subsampling?
-------- -------- -------- xxxxxxxx Theory: Component 2 sampling
-------- -------- xxxxxxxx -------- Theory: Component 1 sampling
-------- xxxxxxxx -------- -------- Theory: Component 0 sampling
0x111121 = 422 (SRAW)
0x111141 = 420 (MRAW)
0x001111 = none (RAW)
+0x090
0x010100 = unused code?
0x000000 = MRAW/SRAW/RAW
+0x094 Sample properties? for SOS header?
---- xxxx ---- ---- ?
---- ---- ---- xxxx Theory: Sample precision
0x000103 = MRAW/SRAW
0x000102 = RAW
+0x098
0x030201 = MRAW/SRAW
0x000201 = RAW
+0x09C
0x111100 = unused code?
0x101000 = MRAW/SRAW
0x001000 = RAW
+0x0E8
-------- -------- xxxxxxxx xxxxxxxx X Resolution (Slice width (px))
+0x0EC
xxxxxxxx xxxxxxxx -------- -------1 Y Resolution (Slice height (px) << 16 | 1)
+0x400-0x430 Some pixel ordering? index table?
+0x440-0x470 Same values as +0x400
MREQ (7D)[]
0xC0820000 MREQ Base (int ID 0x52) +0x304 [32] written with 1, checked for 1 +0x318 [32] written with 0x1C / written with big endian 16 bit word
IPC (7D)[]
This module is for connecting master and slave digics. Not sure about the exact way how it works yet.
Master-side: 0xC0A00000 IPC Base (int ID 0x4F on send/receive, 0x51 on status change) +0x000 [32] CFG +0x008 [32] INT +0x00C [32] INT confirmation? - written with content from +0x08 +0x010 [32] Recv - Received Command +0x014 [32] mBAD - Master Base Address +0x018 [32] sBAD - Slave Base Address +0x01C [32] COM - MasterCommand - read, ORRed with 0x80000000 and further processed +0x020 [32] (compared to content of +0x008) +0x024 [32] Send - Command to send +0x040 [32] VEX +0x044 [32] JEX
Slave-side: same as above, here some memory content 0xC0A00000 IPC Base +0x000 [32] 0x000000E1 +0x010 [32] 0x0000003F +0x020 [32] 0x8000ff81 / 0x48000000 +0x030 [32] 0x00000000 +0x040 [32] 0x00000007
Slave->Master wakeup commands when entering fromutil 0x80000052 (fromutil_ipc_wakeup) 0x80000031 (before entering autoexec.bin) to undo: 0x80000010, then boot normal firmware 0x80000034 or 0x80000030 (before entering FIR load code) to cancel: 0xC8000000, then continue fromutil 0x88000001 (when going to load .FIR) to cancel: 0xC8000000, then continue fromutil 0x98000000 (when going to execute .FIR) 0xB8000000|fir_length (when going to execute .FIR) 0x80000040 (when going to execute .FIR) to cancel: no idea continue fromutil: 0x80000020 (then entering TIO loop) some other details: SendIPCSlaveCommand in Slave is writing id, address and data to 0xC0A00024, ORed with 0xC2000000 for the ID, 0xC4000000 for the length and 0xC8000000 for every 16 bit data word. Interesting is that the address of the buffer containing the data is written there. Does the Master have to pick up that memory on its own?
When booting, the master loops in a IPC check loop that waits for slave to send some data. For every data word the slave sends, the master sets some bits (bitstate) in a global variable. Depending on the bitstate the slave causes, the master enters some state.
IPC command mapping in bootrom: slave sent | bitstate | ipc_get_state returns 0x80000000 | 0x000008 | 0 0x80000010 | 0x000020 | 2 0x80000020 | 0x000040 | 3 0x80000030 | 0x000080 | 10 0x80000031 | 0x000100 | 11 0x80000032 | 0x000200 | 12 0x80000033 | 0x000400 | 13 0x80000034 | 0x000800 | 14 0x80000037 | 0x040000 | 18 0x80000040 | 0x004000 | 17 0x80000041 | -------- | 0x80000042 | -------- | 0x80000043 | -------- | 0x80000050 | 0x008000 | 80 0x80000051 | 0x010000 | 81 0x80000052 | 0x020000 | 0 0x89000012 | 0x100000 | -1 0x89000014 | 0x400000 | -1 0x89000018 | 0x800000 | -1 0x89000020 | 0x000004 | 1 0x89000024 | 0x080000 | -1 0x89000025 | 0x040000 | 18 0x89000026 | 0x000004 | 1 0x90000000 | 0x000008 | 0 0xB0000000 | 0x000008 | 0 0x88000001 | 0x000018 | -1 0x98000000 | 0x000018 | -1 0xB8000000 | 0x000018 | -1 0xC0000000 | 0x000004 | 1 0xD0000000 | 0x000004 | 1
HEAD Timers[]
These timers are used to fire movie mode events like EV_READOUTDONE_INTERRUPT_EVF and EV_SETPARAM_INTERRUPT_EVF.
It seems these timers share the same clock source that is able to run with variable frequency. For 25 FPS modes, the clock source runs with 50 MHz, for 24 FPS modes with 52,7.. MHz on 600D (see VideoTimer)
It looks like the HEAD timers and the video rate timer at 0xC0F06014 are linked in terms of clock source and functionality.
0xC0F07000 [32] SSG Counter (0x01 to restart) 0xC0F07004 [32] 0x01 0xC0F0700C [32] 0x01 to stop/standby 0xC0F07010 [32] 0x3FFF, 0xF000F 0xC0F07014 [32] 0x03 / 0x63 0xC0F07018 [32] 0x7C / 0x1C 0xC0F0701C [32] 0x10 0xC0F07038 [32] 0x00 / 0x01 <- stops processing? 0xC0F0707C [32] 0x00 0xC0F071AC [32] 0x10 / 0x01000010 0xC0F070C8 [32] State 2 Register / VCount? HEAD1 timer: SSG Counter 0xC0F07048 [32] Set to 0x04 to start 0xC0F0704C [32] Set to 0x0C 0xC0F07050 [32] Timer ticks until interrupt (0-0x3FFF) HEAD2 timer: 0xC0F0705C [32] Set to 0x04 to start 0xC0F07060 [32] Set to 0x0C 0xC0F07064 [32] Timer ticks until interrupt (0-0x3FFF) HEAD3 timer: (causing EV_SETPARAM_INTERRUPT_EVF) 0xC0F07134 [32] Set to 0x04 to start 0xC0F07138 [32] Set to 0x0C 0xC0F0713C [32] Timer ticks until interrupt (0-0x3FFF) HEAD4 timer: (causing EV_READOUTDONE_INTERRUPT_EVF) 0xC0F07148 [32] Set to 0x04 to start 0xC0F0714C [32] Set to 0x0C 0xC0F07150 [32] Timer ticks until interrupt (0-0x3FFF)
Video timer[]
They control the frame rate for reading out the CMOS sensor and processing, displaying and recording.
0xC0F06000 Video timers
+0x000 [32] Trigger coherent update
+0x004 [32] 0=standby, 1=readout
+0x008 [32] T0 - Frame rate timer pre-divider register.
Depending on camera model the input clock is 24, 28.8 or 32MHz
+0x00C [32] (should be same as +0x08)
+0x010 [32] (should be same as +0x08)
+0x014 [32] T1 - Timer reload value for sensor sampling (FPS)
This will divide the pre-divided clock down to final rame rate.
+0x084 [32] (0x0001007E, written with regs 08, 0C, 10 and 88)
+0x088 [32] Video Y-Resolution related?
0x049E042E: 1182|1070 for 1920x1080 and 640x480
0x0418044E: 1048|1102 for 1920x1080 digital zoomed
0x02D0042E: 720|1070 for 1280x720
maybe "scanline" clock?
Frame rate calculation:
-----------------------------
clk1 = BaseClk / (T0 + 1)
fps = clk1 / (T1 + 1)
BaseClk = 24.0 MHz for 5D II
BaseClk = 28.8 MHz for 600D, 550D, 50D, 60D
BaseClk = 32.0 MHz for 500D
clk1 is also used for HEAD3/HEAD4 event generation. (0xC0F0713C, 0xC0F07150)
(see google spreadsheet http://bit.ly/HXmy8X)
ASIF[]
ASIF requires clock bits 0x02000000 and 0x00000004 to be enabled in CLOCK_ENABLE register at 0xC0400008 before it can work.
0xC0920000 ASIF Base
+0x000 [32] Enable register
+0x004 [32] Init: 0x01
+0x008 [32] Init: 0x01
+0x00C [32] Init: 0x01
+0x010 [32] set to 1 StartASIFforObserve, Init: 0x01
+0x100 [32] set to 0 StartASIFforObserve, Init: 0x00
+0x118 [32] set to 1 on ADC start
+0x11C [32] ADC Audio mode
---------------1 UINT8
--------------1- Interleaved mode (stereo)
-------------1-- INT16
+0x120 [32] Transfer start ADC
+0x204 [32] Init: 0x00
+0x208 [32] Init: 0x00
+0x20C [32] set to 1 on DACstart
+0x210 [32] DAC Audio mode
---------------1 UINT8
--------------1- Interleaved mode (stereo)
-------------1-- INT16
+0x220 [32] Transfer start DAC
+0x238 [32] Read during initializing +0x004, then set to 0x01
+0x320 [32] Init: 0x07
0xC0500000 ASIF DMA Controller
+0x20 DAC 0x80808080/0x00000000 depending on uint16/uint8
+0x24 DAC set to 8
+0x80 ADC current buffer
+0x84 ADC current transfer count
+0x88 ADC next data buffer
+0x8C ADC next transfer count
+0x90 ADC buffer status?
Set to 0x23/0x21 on start DAC, 0x00 on stop
----------100001 base value
--------------1- Set when a "next buffer" is set
+0x94 ADC INT status
+0xA0 DAC current buffer
+0xA4 DAC current transfer count
+0xA8 DAC next data buffer
+0xAC DAC next transfer count
+0xB0 DAC buffer status
Set to 0x27 on start DAC, 0x00 on stop
+0xB4 DAC INT status
KAISER[]
This seems to be some hashing hardware extension used in 7D, 5D3 and maybe others.
On 7D and 5D3 the EDMAC connection ID is 0x15.
0xC0F02000 Kaiser Base
+0x000 [32] Enable register
---------------1 Enable
1--------------- Init
+0x004 [32] Initialized with 0x00 for MD5, 0x30 for SHA256
/* MD5 init values */
+0x014 [32] Initialized with 0x67452301
+0x018 [32] Initialized with 0xEFCDAB89
+0x01C [32] Initialized with 0x98BADCFE
+0x020 [32] Initialized with 0x10325476
/* SHA init values */
+0x014 [32] Initialized with 0x6A09E667
+0x018 [32] Initialized with 0xBB67AE85
+0x01C [32] Initialized with 0x3C6EF372
+0x020 [32] Initialized with 0xA54FF53A
+0x050 [32] Initialized with 0x510E527F
+0x054 [32] Initialized with 0x9B05688C
+0x058 [32] Initialized with 0x1F83D9AB
+0x05C [32] Initialized with 0x5BE0CD19
+0x024 [32] Initialized with 0x00
+0x030 [32] Initialized with 0x04
+0x034 [32] Initialized with 0x04
+0x038 [32] 32 bit digest A
+0x03C [32] 32 bit digest B
+0x040 [32] 32 bit digest C
+0x044 [32] 32 bit digest D
+0x048 [32] State register
+0x04C [32] Initialized with 0x00 for MD5, 0x01 for SHA256
+0x060 [32] 32 bit digest E
+0x064 [32] 32 bit digest F
+0x068 [32] 32 bit digest G
+0x06C [32] 32 bit digest H
EDMAC[]
EDMAC means "Engine DMA Controller" (CHDK project, firmware strings) and transfers data from image preprocessing modules into SDRAM and between SDRAM memory areas.
When setting the destination address, its relative to SDRAM start. This means, addresses start at 0x00000000.
Every EDMAC has a source or destination connection, depending on whether it is a write or read channel. Write channels read from their source connection (imagine the connection number is like the data bus where it reads data from) and writes the data into the specified memory address. Read channels read data from the specified memory address and pass it to the assigned destination connection.
The connections, source and destination, are numbers from 0 to 31 where different hardware devices read from or write data to, depending on their setup. For example connection 0 is only used for CRAW transfer from the sensor. So there is some hardware that will send the CRAW stream just to channel 0. When some EDMAC channel is reading from that connection, then the data can be used. When a read channel is reading from RAM and writing to connection 0, it will most likely disturb the write channel that is expecting CRAW data on this connection.
Some devices like the JPCORE can be set up to read or write from/to connections depending on the mode they work in. When decompressing a JPG, the JPCORE is likely to get set up for reading from connection 5, decompressing the image and writing the result to channel 3 or 4. When compressing an image, it is configured the other way: reading from 3 or 4 and writing to 5.
When choosing a connection that has no device listening on it, still some other EDMAC channels will read or write. This means we can use unused connections for stuff like memcpy using EDMAC.
For vignetting shading correction, something like a addition/multiplication path is used by setting write edmac 1 to read from connection 0x10, read edmac 41 to write to connection 1 and read edmac to connection 0. EDMACs 1 and 40 use the same size, so one is probably input from RAM, the other is output to RAM.
Some details about for what the offsets and ya/yb/xa/xb etc. are meant for, the patent at https://www.google.de/patents/US7817297 might explain most of it - especially figure 11A.
EDMAC0 - EDMAC15
0xC0F04000
0xC0F04100
..
0xC0F04F00
+0x00 [32] DMA control
-------- -------1 Start transfer / Transfer in progress
+0x04 [32] flags
-------- -----xxx -------- -------- flags for read channels when calling StartEDmac
-------- -------- -------- xx------ flags for write channels when calling StartEDmac
xxx----- -------- ---x---- -----xxx flags for SetEDmac (but you can set any bit)
1------- -------- -------- -------- only one transfer, causes errors on other DMAs
-10----- -------- ---1---- -------- 16 byte per transfer
-01----- -------- ---1---- -------- 8 byte per transfer
-10----- -------- ---0---- -------- 4 byte per transfer
-01----- -------- ---0---- -------- 2 byte per transfer
+0x08 [32] SDRAM destination offset
+0x0C [32] ((yn << 16) | xn) & 0x0FFF1FFF
+0x10 [32] ((yb << 16) | xb) & 0x7FFFFFFE
+0x14 [32] ((ya << 16) | xa) & 0x0FFF1FFF
+0x18 [32] off1b & 0x0001FFFE if DIGIC <= 4 else 0x0007FFFE
+0x1C [32] off2b & 0x0FFFFFFE if DIGIC <= 4 else 0xFFFFFFFE
+0x20 [32] off1a & 0x0001FFFE if DIGIC <= 4 else 0x0007FFFE
+0x24 [32] off2a & 0x0FFFFFFE if DIGIC <= 4 else 0xFFFFFFFE
+0x28 [32] off3 & 0x0FFFFFFE if DIGIC <= 4 else 0xFFFFFFFE
off1*: signed, 17 bits for DIGIC 4 or lower, 19 bits for DIGIC 5.
off2*: signed, 28 bits for DIGIC 4 or lower, 32 bits for DIGIC 5.
+0x30 [32] interrupt reason (read on interrupt)
0x01 = normal? (used with PackMem)
0x02 = normal (transfer finished)
0x04 = pop (memsuite finished?)
0x10 = abort
+0x34 [32] 3 = AbortEDmac
+0x40 [32] (fencing uses it and sets it to 0x23 which might be a connection)
Current assumption:
(
((xa, skip off1a) * ya, xa, skip off2a) * xn
(xb, skip off1b) * ya, xb, skip off3
) * yn,
(
((xa, skip off1a) * yb, xa, skip off2b) * xn
(xb, skip off1b) * yb, xb, skip off3
)
Previous assumption:
xb: block size - number of bytes per copy operation
this number must be >1 and a multiple of two (write) or four bytes (read)
after this number of bytes were transmitted, an commit command is issued.
write channels wait for a commit command before the block is written into memory fully.
yb: block count | number of blocks to transfer
xn: transaction count | how often above should get transferred
ya: same as xb when more transactions?
off2b: padding (positive) or cropping (negative) at the right edge
EDMAC16 (7D, Digic 4)
0xC0F27000
..
EDMAC16 - EDMAC31 (5D3, Digic 5)
0xC0F26000
0xC0F26100
..
0xC0F26F00
EDMAC32 - EDMAC47 (5D3, Digic 5)
0xC0F30000
0xC0F30100
..
0xC0F30F00
EDMAC usage: 5D3
CAPTURE:
0x03 - OHYE[W]
0x04 - AE1[W]
0x10 - AF[W]
0x20 - AE2[W]
0x15 - SRKA1[W]
0x16 - SRKB1[W]
0x13 - SRKA2[W]
0x14 - SRKB2[W]
0x12 - MEM1[W]
0x18 - HIV[R]
0x0B - DEFM[R]
SSDEVELOP:
0x15 - YUV[W]
0x06 - ALO[W]
0x0A - JUKAI[W]
0x09 - OHYE[R]
0x1A - SUSA[R]
0x1B - SUSB[R]
VRAM:
0x00 - VRAM[W]
0x05 - VRAM[W]
0x02 - NV12[W]
0x16 - NV12[W]
0x01 - JPEG[W]
0x1C - YUV[R]
0x08 - TA10[R]
EDMAC usage: 600D (info at 0x2BAB4)
00 - WriteEDmacWbInteg
01 -
02 - WriteEDmacYuv
03 - WriteEDmacVram
04 - WriteEDmacPackMem, EffectPs
05 - WriteEDmacFenYuv
06 - WriteEDmacFen_B
07 -
08 - ReadEDmacDefCorre
09 - ReadEDmacHivshd_V_, EffectPs
10 - ReadEDmacYuv maybe
11 -
12 - ReadEDmac_
13 - ReadEDmacVram maybe
14 -
15 -
16 - WriteQuarkEDmac
17 -
18 - CRaw DMAC?
WRITE-EDMAC Connections
0xC0F05000 [32] WREDMAC00
0xC0F05004 [32] WREDMAC01
..
0xC0F0501C [32] WREDMAC16 (would be WREDMAC7, but that seems unused)
0xC0F05020 [32] RDEDMAC0 (would be WREDMAC7, but that seems unused)
..
0xC0F05200 [32] WREDMAC17
..
0xC0F0523C [32] WREDMAC31
EDMAC-Connections: (W:WriteEDMAC connected, R:ReadEDMAC connected)
0x00 - W:CRaw data
0x01 - R:ObAreaCopyPath
0x02 - W:WB Execute, WbInteg
0x03 - [JPCORE] RAW/JPEG input (depending on mode)
0x04 - [JPCORE] YUV output, W:FilteringCompositePath
0x05 - [JPCORE] Encoded data
0x06 - (used for memcpy operations)
0x07 - (used for memcpy operations)
0x08 - R:"Ltkids Shrek"
0x0A - R:AddPonyPath, DetectAbberationPath.c, W:ObAreaCopyPath
0x0C - R:AddPonyPath, R:ColorSubPath, DetectAbberationPath.c
0x0D - W:ColorSubPath, DetectAbberationPath.c
0x0E - R:ProcessFencingC
0x0F - R:CaptureImagePath
0x10 - W:ObAreaCopyPath, Flicker
0x11 - R:ProcessFencingA
0x12 - W:ProcessFencingA
0x13 - W:DevelopPathAddPonyPath
0x15 - [JPCORE] Input data for MJPEG DecRotate, output on 0x05
0x1B - [JPCORE] R:FilteringCompositePath
0x1C - OhyITG, MidInteg
0x1F - W:"Ltkids Shrek"
0x20 - W:"Ltkids Shrek"
0x21 - W:"Ltkids Shrek"
0x22 - W:"Ltkids Shrek"
0x23 -
0x35 - W:AE Execute
EDMAC-Connection groups: (which camera? 600D?)
AddPonyPath:
W: 0x13
R: 0x0A, 0x0B
AffineYuvPath: (rotation?)
W: 0x0D
R: 0x0B
GainBlendYuvPath:
W: 0x1A
R: 0x03, 0x0C
Ltkids Shrek:
W: 0x1F, 0x20 or 0x21, 0x22
R: 0x08, 0x08
EDMAC-Connection groups: (5D3)
DEFM:
R: 0x08, 0x0F
W: 0x00
WDMAC32_ISEL(2) ADMERG
DEFD:
R: 0x01
W: 0x00
WDMAC32_ISEL(1) DS_SEL(0)
DEFC:
R: 0x01
W: 0x10
WDMAC16_ISEL(0) DS_SEL(0) PACK16_ISEL_set(4) PACK16_ISEL2(0)
SUB:
R: 0x01, 0x34 (dark frame)
W: 0x10
no ISEL, but using ADUPNACK, DSUNPACK, DARK, PACK16
OB:
R: 0x01
W: no, data is in registers
DS_SEL(0) OBINTG_ISEL(6)
TTJ:
R: 0x03
W: 0x05
OPE:
R: 0x00, 0x01
W: 0x01
PROC24_ISEL(3) PROC24_ISEL_2(0) DS_SEL(0), using DSUNPACK, DARK, UNPACK24
Hivshd:
R: 0x01, 0x0F (for shade data)
W: 0x10
WDMAC16_ISEL(0) DS_SEL(0) PACK16_ISEL(7) PACK16_ISEL2(0)
DSUNPACK:
ISEL 0: conn#1
WDMAC16:
ISEL 0: PACK16
PACK16:
ISEL 4: DSUNPACK
ISEL 7: HIVSHD
WDMAC32
ISEL 0: (raw dark frame, like photo)
ISEL 1: (DSUNPACK, DEFD)
ISEL 2: (ADMERG)
ISEL 4:
PACK32:
ISEL 1:
ISEL 5: (raw dark frame, like photo)
PROC24:
ISEL 14:
DMA[]
Copied from DMA
DMA channel #3 seems to be unused on 600D v1.0.1 and can be used for Magic Lantern.
0xC0A10000 DMA channel 0
+ 0x00 [32] Control register
0x80000000 to reset and disable
0x00000001 to enable
+ 0x04 [32] unknown, written with 0x00 on DMA setup (2 LSB must be 0, others dont care)
+ 0x08 [32] control bits
-------- ------1- -------- -------1 written to start transfer
-------- -------- -------- -------1 start transfer
-------- -------- -------- ---1---- decrease source address
-------- -------- -------- --1----- dont modify source address
-------- -------- -------- -1------ decrease destination address
-------- -------- -------- 1------- dont modify destination address
-------- -------1 -------- -------- gets set when (delta(source,dest) & 0x1F) != 0. maybe some cache line issues?
-------- ------1- -------- -------- set when starting transfer. enable interrupt flag?
1------- -------- -------- -------- reverse words LE<->BE
+ 0x10 [32] unknown, written with 0x00 on DMA setup
is checked for 0x06 in interrupt handler and set to 0x00
+ 0x14 [32] unknown, written with 0x07 on DMA setup (only 3 LSB used?)
not used when copying without interrupt
+ 0x18 [32] source address
+ 0x1C [32] destination address
+ 0x20 [32] transfer count (ignoring 2 LSB)
0xC0A20000 DMA channel 1 (see above)
0xC0A30000 DMA channel 2 (see above)
0xC0A40000 DMA channel 3 (see above, seems to be unused)
Timer/Clock Module[]
Timer #0 (unused)
0xC0210000
Timer #1 (unused)
0xC0210100
Timer #2 (used as 10ms system timer)
0xC0210200 [32] Control register
0x80000000 to reset and disable
0x00000001 to enable
0xC0210204 [32] (written with 0x02)
0xC0210208 [32] Timer reload value (1µs resolution)
0xC021020C [32] Timer current value?
0xC0210210 [32] Interrupt enable (?)
0xC0210214 [32] (written with 0x03)
Another Timer
0xC0242010 [32] Control register
---------------1 enable flag
----xxxx-------- predivider
1 = 3.000 MHz tick rate
2 = 2.250 MHz tick rate
3 = 1.125 MHz tick rate
4 = 1.000 MHz tick rate (default)
0xC0242014 [32] 12 bit counter. used for task load measurement.
Before the timer module will start working, we have to enable the clock
distribution to this modules using these registers.
0xC0400004 [32] Clock selection
Bitmask
0x03000000 SD/MMC clock selection bits
0 unknown
1 16MHz
2 24MHz
3 48MHz
0xC0400008 [32] Clock control
Bitmask - configures which module gets system clock
0x00000002 Engio LCLK
0x00000004 (ASIF related too)
0x00000008 SD/MMC clock 1
0x00000100 Display PWM module
0x00000400 Timer #0
0x00000800 Timer #1
0x00001000 Timer #2
0x00010000 LCLK (also set)
0x00200000 SIO clock
0x01000000 DMA module #0 (fIPCClk)
0x01000000 IPC module on 7D
0x02000000 ASIF
0x10000000 SD/MMC clock 2
0xC0400010 [32] (Timer #0?)
0xC0400014 [32] (Timer #1?)
0xC0400018 [32] (Timer #2?) written with 0x00
0xC0400044 [32] HClk (from 5D Mk1)
0xC0400048 [32] LClk (from 5D Mk1)
0xC040004C [32] MClk (from 5D Mk1)
0 = Full clock (72 MHz on 5D)
1 = Half clock (36 MHz on 5D)
3 = Quarter clock (18 MHz on 5D)
When switching the clock rate max->min or reverse, always go over half clock.
0xC0400088 [32] USB PHY - written with 0x030101 ("Xtalless DD")
0xC040008C [32] USB PHY - written with 0x000001
0xC04000AC [32] PLL flags
0x00000004 (PLLH enable)
0x00000008 (PLLV enable)
0xC04000B4 [32] PSEL
0xC0400704 [32] MSCLK Enable
Another unknown control register is this one, maybe it has to do with
interrupt priorities?
0xC0203000 [32] Timer #0 related
0xC0203004 [32] Timer #1 related
0xC0203008 [32] Timer #2 related (initialized with 0x08)
HP timers[]
Microsecond timers: SetHPTimerAfterNow / SetHPTimerNextTick
These are 8 timers sharing the same interrupt. First timer is at 0xC024326x, last is at 0xC02432Ex.
Setting a timer (5D2 212, x is from 0x6 to 0xD):
[HPTimer] at [0xFF9B3678] [0xC02432x0] <- 0x0 [HPTimer] at [0xFF9B3648] [0xC02431x0] <- 0x0 (timer stop?) [HPTimer] at [0xFF9B35D0] [0xC02431x4] -> ??? [HPTimer] at [0xFF9B35D0] [0xC02431x4] <- timer_value (absolute time?); bit 0x100000 is kept [HPTimer] at [0xFF9B3698] [0xC02432x4] <- 0x0 [HPTimer] at [0xFF9B3698] [0xC02432x4] -> 0x0? [HPTimer] at [0xFF9B3638] [0xC02431x0] <- 0x1 (timer start?) [HPTimer] at [0xFF9B3658] [0xC02432x0] <- 0x1
HP timer interrupt is 0x10 (OC4_14). Let's see what happens there.
C0243300 read, masked with 0x3FFFFF => which timer triggered the interrupt?
0x10 => timer ID 6
0x40 => timer ID 7
...
0x40000 => timer ID 0xD
0 => no more timers (required for the interrupt loop to finish)
C02431x0: set to 0 (stops the timer?)
C02432x4: set to 0, then read back (seems to return always 0)
if this timer should retrigger:
C02431x0 and C02432x0: set to 0
C02431x4: timer value goes here; bit 0x100000 is kept
C02432x4: set to 0, then read back (seems to return always 0)
C02431x0 and C02432x0: set to 1
loop until C0243300 returns 0
GPIO Ports[]
There are GPIOs at 0xC0220000 and eventually "Advanced GPIO" at 0xC022D000/0xC022F000 (5DII a lot, 600D also some).
These at 0xC0220000 are well documented here, the others are still unclear at the moment.
GPIO ports start at 0xC0220000 and are 32 bit words per GPIO.
Only up to 9 bits seem to be used.
For every 4 GPIOs, there is one config register at 0xC0221000.
GPIO_EXST address = (0xC0220000 + 4*[GPIO_num])
GPIO_FSSEL address = (+ 0x1000 - 0x107C)
GPIO_BUSSEL address = (+ 0x1110, 0x1128, 0x112C, 0x1114, 0x1118, 0x111C, 0x1120)
GPIO_OPSEL address = (+ 0x1200 - 0x12C0)
GPIO_OPSEL address = (+ 0x1800 - 0x187C)
GPIO bits:
------------------------------
0xC0220000 [32] GPIO state
-------- -------x Input level. Set when port pin is high.
-------- xxxxxxx- port configuration mask
-------- ------x- Output level (0 = low, 1 = high)
-------- ----xx-- Port mode (00 = IN, 01 = OUT, 10 = FS, 11 = BUS)
-------- --x----- Pull up mode (0 = pull down, 1 = pull up)
-------- -x------ OFF bit - no pull up/down?
-------- x------- Unknown. Read only bit.
-------x -------- Unknown. Set on some in and some out ports
Config bits:
------------------------------
-------- ---xxxxx Used, Unknown
GPIO usage on 7D on slave side: 0xC0220024 [32] GPIO__: [IN] Master is ready? some negotiation 0xC0220094 [32] GPIO__: [OUT] ICU->MPU reboot? 0xC022D0D0 [32] GPIO__: [OUT] Used for comm with master 0xC022D0F8 [32] GPIO__: [OUT] Used for comm with master (= 0x00138800 / 0x00038C00) 0xC022D06C [32] GPIO__: [OUT] CF Card LED (= 0x00138800 / 0x00038C00) GPIO usage on 5DMkIII: 0xC0220150 [32] GPIO__: [IN] HDMI connected 0xC0220164 [32] GPIO__: [IN] headphone connected 0xC022016c [32] GPIO__: [IN] external mic connected 0xC0220174 [32] GPIO__: [IN] video out connected 0xC0220030 [32] GPIO__: [OUT] CMOS CS 0xC02200A0 [32] GPIO__: [OUT] ADTG2 CS 0xC02200A4 [32] GPIO__: [OUT] ADTG4 CS GPIO usage on 600D: 0xC0220000 [32] GPIO00: [OUT] EEPROM ctrl: 0x48 before, 0x44 after data write 0xC0220004 [32] GPIO01: [OUT] EEPROM ctrl: 0x48 before, 0x44 after data write 0xC0220008 [32] GPIO02: [OUT] ADTG CS: 0x44 before, 0x46 after data write 0xC0220014 [32] GPIO05: [IN] VSW_ON High 0xC0220018 [32] GPIO06: [OUT] EEPROM ctrl: 0x46 before, 0x44 after data write 0xC0220028 [32] GPIO10: [OUT] DISP CS: 0x44 before, 0x46 after data write 0xC0220034 [32] GPIO13: [IN] USB connected 0xC0220070 [32] GPIO28: [IN] Video connected 0xC022009C [32] GPIO39: [OUT] Set low when starting SIO3 communication to T19x 0xC02200E8 [32] GPIO58: [IN] Mic connected 0xC0220108 [32] GPIO66: [IN] Erase SW jumper enabled 0xC022010C [32] GPIO67: [OUT] Display enabled. Maybe some display voltage (0=disable, 1=enable) 0xC0220118 [32] GPIO70: [OUT] Display enabled, disabled ~200ms later than GPIO67. 0xC022012C [32] GPIO75: [OUT] CMOS CS: 0x46 before, 0x44 after data write 0xC0220130 [32] GPIO76: [OUT] SND CS: 0x44 before, 0x46 after data write 0xC0220134 [32] GPIO77: [OUT] SD/CF Led drive output 0xC0220138 [32] GPIO78: [IN] HDMI connected
Some comments about "Advanced GPIO":
the 0xC022D0000 addresses look like set-reset IO ports.
___ LED pin high
/ ___ LED pin low
| /
LED_ON: 0001 0011 1000 0000 0000 0000
LED_OFF: 0000 0011 1000 0100 0000 0000
|----------->|
when setting the "set port" bit, the port is enabled, when setting "clear port" bit, output is disabled. in the slave-master comm routine, 0xF8 is accessed two times - once when saying "wait WakeUp Slave" and then the code waits for a GPIO being set (GPIO09). at the end of the routine, 0xF8 is accessed again and it waits for GPIO09 being cleared.
0xF8_A: 0000 0011 1000 1100 0000 0000
0xF8_B: 0001 0011 1000 1000 0000 0000
|----------->|
as you see, the same constellation. first clear and later set. the '1' bit left of the clear (marked green) is perhaps another I/O that is permanently cleared on every access.
when looking at 0xD0 that is also written, it is one bit left of the 0xF8 and LED bit position. so i guess the set/clear bits have a 9 bit distance and there are more than just one I/O per 32bit register.
0xD0: 0010 0011 1000 0000 0000 0000 <- found in code
0xD0: 0000 0011 1000 1000 0000 0000 <- maybe for resetting this IO line? just a guess!!!!
|----------->|
when writing 0xE000... to this register, it is perhaps "tristate bank" or smth like that.
Bufcon[]
This area looks like another GPIO region which is dumped in EOS M and 700D bootloader. (Possibly every other rebel newer than the EOS M)
GPIO bits for 0xC022C000 (EOS M and 700D)
------------------------------
0xC022C000 [32] IO Port configuration
-------- -------x Port mode (1 = OFF_H, 0 = OFF_L)
-------- ------x- Port mode (1 = IN, 0 = OFF)
-------- -----x-- 1 = pull up, 0 = pull down
-------- ----x--- GPIO_OFF
-------- -xx----- Port mode (11 = OUT, 00 = IN or OFF)
-------- x------- GPIO_OFF
0xC022C??? - 0xC022C02C [700D] CF_IORD, CF_IOWR, CF_WE, CF_CD0, CF_CD1, CF_CE2, CF_INT, CF_OE, CF_WAIT, CF_CE1, CCDCLK
0xC022C030 - 0xC022C05C [700D] -- not dumped --
0xC022C060 - 0xC022C078 SSG_xx
0xC022C07C - 0xC022C098 ELCYB_xx
0xC022C09C - 0xC022C0A8 ELCYCLK, ELCYH, ELCYV, TGCLK
0xC022C0AC - 0xC022C1E8 GPIO_xx
0xC022C1EC - 0xC022C1F8 MON_xx
0xC022C1FC - 0xC022C208 DSPL, DSPR, RXD0, TXD0
0xC022C20C - 0xC022C238 [700D] -- not dumped --
0xC022C23C - 0xC022C244 ROMCE, ROMOE, ROMWE
0xC022C248 - 0xC022C284 ROMD_xx
0xC022C288 - 0xC022C2E0 ROMA_xx
0xC022C500 [32] Drive strength configuration
-------- ----xxxx DRVP power in mA
-------- xxxx---- DRVN power in mA
------xx -------- speed (00 = fastest, 01 = fast, 10 = slow, 11 = slowest)
-----x-- -------- EFUSE (1 = P-only, 0 = PVT)
Interrupts[]
0xC0201000 ID that caused interrupt (ID already shifted left by 2) (7D Master) 0xC0201004 ID that caused interrupt (ID already shifted left by 2) 0xC0201010 re-/enable interrupt by writing its ID
Status Registers[]
0xC0F070DC [32] HEAD error status
...----------1-- CCD Shifter error occurred
...---------1--- FIFO error occurred
...--------1---- AF Shifter error occurred
EEKO - Second core in Digic5[]
0xC022320C [32] Clock control
---------------x Either enable processor clock or set processor reset (low-active)
-------------xx- Enable memory clock
0xC0223210 [32] Unknown
Set to 0x7E on init
Misc Registers[]
0xC0F2411C [32] some bits set when cartridge not initialized/ready
0xC022301C [32] SD related
---------------x When this bit is set, the SD card slot is empty (to be verfified)
0xC0800000 [32] Serial terminal TX byte
0xC0800004 [32] Serial terminal RX byte
0xC0800014 [32] Status lines
---------------x When this bit is set, RX byte can be read. must be set to clear RX flag
--------------x- When this bit is set, the TX byte gets transmitted. gets cleared after transmission
0xC022F480 [32] Other VSW Status
0x40000 /VSW_OPEN Hi
0x80000 /VSW_REVO Hi
PWM module (600D):
0xC0238060 [32] Display PWM init (written with 0x02)
0xC0238064 [32] Display PWM 0x00(dark) - 0xFF(bright)
PWM module (7D):
0xC0238000 [32] Display PWM init (written with 0x02)
0xC0238004 [32] Display PWM 0x00(dark) - 0xFF(bright)
Audio related:
0xC092xxxx ASIF ADC (Analog Digital converter). playing 8/16 signed/unsigned audio?
0xC050xxxx DMA DA or AD
LiveView related:
0xC0F14078 set to 0x01 on vertical blank (reset-on-read, so don't read it); on 5Dc, write 1 to it to apply palette changes (0xC0F14080 - 0xC0F140BC).
0xC0F140C0 does luma scaling
0xC0F140C4 does chroma scaling
0xC0F140C8 sets the bmp overlay mode
0xC0F140E8 [s32] pixels to skip - causes distorted image
0xC0F140F0 [s32] pixels to skip - causes distorted image
0xC0F37010 switches between JP57 (0x40000 - 5D3) and JP51 (0xC0000 - 700D)
0xC0F37014 LV raw type (see lv_af_raw, lv_set_raw) on DIGIC5 (DIGIC4 uses PACK32_ISEL)
0xC0F371FC unpacking mode (see PACK16_MODE) for the input module that feeds image data to lossless encoder
0xC0F06084 RAW first line|column. Column is / 2. 600D: 0x0001007E
0xC0F06088 RAW last line|column. 600D: FHD 1182|1070, 3x 1048|1102, HD 720|1070
0xC0F06800 RAW first line|column. Column is / 8 on 5D3 (parallel readout?)
0xC0F06804 RAW last line|column. 5D3: f6e|2fe, first 1|18 => 5936x3950
0xC0F09050 Aewb metering area (y1|x1)
0xC0F09054 Aewb metering area (y2|x2)
0xC0F383D4 Preview area (y1 << 16) | (x1/4), similar to raw_info.active_area (5D3)
0xC0F383DC Preview area (y2 << 16) | (x2/4)
SIO Registers (serial IO)[]
/* these registers are accessed with 32 bit accesses, but most of them contain 16 bit data only */
SIO0 (ADTG on 5D3)
---------------------------
0xC0820004 [32] SIO0 flags
...------------1 Busy flag
Set this bit when data to write should be transmitted
SIO controller will clear this bit if its done
0xC082000C [32] SIO0 setup register (maybe leading clocks, polarity, phase etc)
The lowest bits are the bit count (8 LSB?)
0xC0820014 [32] SIO0 setup register (maybe clock speed?)
set to 0x00000111 for "ADTG"
0xC0820018 [32] SIO0 TX-Data
0xC082001C [32] SIO0 RX-Data
SIO1 (sound chip, RTC)
---------------------------
0xC0820104 [32] SIO1 flags
...------------1 Busy flag
Set this bit when data to write should be transmitted
SIO controller will clear this bit if its done
0xC082010C [32] SIO1 setup register (maybe leading clocks, polarity, phase etc)
The lowest bits are the bit count (8 LSB?)
set to 0x800A0300 before reading "SND" (may have no effect, overwritten later)
set to 0x800A0308 before reading "SND"
set to 0x800A0310 before writing "SND"
set to 0x800E0610 for "DISPSTATE" (brightness etc?)
0xC0820114 [32] SIO1 setup register (maybe clock speed?)
set to 0x00000000 after writing "SND"
set to 0x00000111 for "DISPSTATE" (brightness etc?)
0xC0820118 [32] SIO1 TX-Data
0xC082011C [32] SIO1 RX-Data
SIO2 (CMOS, ADTG, EEPROM)
---------------------------
0xC0820204 [32] SIO2 flags
...------------1 Busy flag
Set this bit when data to write should be transmitted
SIO controller will clear this bit if its done
0xC082020C [32] SIO2 setup register (maybe leading clocks, polarity, phase etc) default: 0x10000000
The lowest bits are the bit count (8 LSB?)
set to 0x00020210 before writing "CMOS" (16 bit writes)
set to 0x000A0220 before writing "ADTG" (32 bit writes)
set to 0x1002061B before writing "EEPROM" (may have no effect, overwritten later)
set to 0x1002060B before writing "EEPROM" (upper 11 bits)
set to 0x10000610 before writing "EEPROM" (lower 16 bits)
0xC0820210 [32] SIO2 unknown
...------------1 Bit cleared during init
0xC0820214 [32] SIO2 setup register (maybe clock speed?)
set to 0x00000115 before writing "CMOS"
set to 0x00000111 before writing "ADTG"
set to 0x00000115 before read/write "EEPROM"
0xC0820218 [32] SIO2 TX-Data - CMOS/ADTG/EEPROM data to write (16 bit data length)
0xC082021C [32] SIO2 RX-Data - EEPROM data that was read (16 bit data length)
SIO3 (intercom) IRQ 0x36
---------------------------
0xC0820304 [32] SIO3 flags
...------------1 Busy flag
Set this bit when data to write should be transmitted
SIO controller will clear this bit if its done
0xC0820308 [32] SIO3 unknown. written with 0x01 before interrupt setup for comm. maybe IE flag.
0xC082030C [32] SIO3 setup register (maybe leading clocks, polarity, phase etc)
The lowest bits are the bit count (8 LSB?)
set to 0x13020010 before writing "LENS"
0xC0820318 [32] SIO3 TX-Data
0xC082031C [32] SIO3 RX-Data
SIO3 ? (600d 1.0.1 at sub_FF1DB44C)
------
0xC02000AC (see FF1DB5C8)
0xC0A00024 (7D IPC Tx)
0xC0820310 (see sub_FF1DB3B4)
Cartridge stuff[]
This module seems to be a queue of registers and data to write at.
Path code is feeding some registers and their target values into the cardridge and when the frame is going to be exposed, cartridge will write all registers immediately.
0xC0F24100 [32] CARTRIDGE_USE
write 0x0F -> cmd: CARTRIDGE_USE
0xC0F24104 [32] CARTRIDGE1_ADDR / "WriteAddressData"
e.g. 0xC0F16010, 0xC0F16014, 0xC0F15080, 0xC0F150C0
0xC0F24108 [32] CARTRIDGE1_DATA / "WriteData"
0xC0F2410C [32] CARTRIDGE1_CMD
cmd: 0x01 -> cartridge_start
cmd: 0x03 -> cmd: CARTRIDGE1_CMD_USE
cmd: 0x04 -> cmd: reset/finish
0xC0F24110 [32] CARTRIDGE1_OC_EN
write 0x00 -> cmd: CARTRIDGE1_OC_EN
0xC0F2411C [32] Flags? Waiting for 0x00 after cmd 0x01
Image PreProcessing[]
These addresses are used to process the 14 bit raw image stream.
There are various use cases, some are for dark current compensation, some for converting to 16 bit etc. We don't access them directly yet, but we are able to call some routines that make use of these modules.
0xC0F08000 - DARK Control Register
0xC0F08004 - DARK_MODE (bitmask of bits 0x113117F)
0xC0F08008 - DARK_SETUP (mask 0x7FF signed integer!!) (brightens or darkens frame, overwrites DARK_SETUP_14_12)
0xC0F0800C - DARK_LIMIT (mask 0x3FFF) (no noticeable change)
0xC0F08010 - DARK_SETUP_14_12 (mask 0x07FF) (brightens up frame, overwrites DARK_SETUP)
0xC0F08014 - DARK_LIMIT_14_12 (mask 0x0FFF) (no noticeable change)
0xC0F08018 - DARK_SAT_LIMIT (mask 0x3FFF) (no noticeable change)
0xC0F08020 - SHAD Control Register
0xC0F08024 - SHAD_MODE (mask 0x111F)
0xC0F08028 - SHADE_PRESETUP (mask 0x7FF)
0xC0F0802C - SHAD_POSTSETUP (mask 0x1FFF)
0xC0F08030 - SHAD_GAIN (mask 0x1FFF)
0xC0F08034 - SHAD_PRESETUP_14_12 (mask 0x1FFF)
0xC0F08038 - SHAD_POSTSETUP_14_12 (mask 0x7FFF)
0xC0F08040 - TWOADD Control register
0xC0F08044 - TWOADD_MODE
0xC0F08048 - TWOADD_SETUP (mask 0x7FF)
0xC0F0804C - TWOADD_LIMIT (mask 0xFFF)
0xC0F08050 - TWOADD_SETUP_14_12 (mask 0x1FFF)
0xC0F08054 - TWOADD_LIMIT_14_12 (mask 0x3FFF)
0xC0F08058 - TWOADD_SAT_LIMIT (mask 0x3FFF)
0xC0F08060 - DSUNPACK Control Register
0xC0F08064 - DSUNPACK_MODE
0xC0F08070 - UNPACK24 Control Register
0xC0F08074 - UNPACK24_MODE
0xC0F08080 - ADUNPACK Control Register
0xC0F08084 - ADUNPACK_MODE (mask 0x131)
0xC0F08090 - PACK32 Control register
0xC0F08094 - PACK32_MODE
0xC0F080A0 - DEF Control register
0xC0F080A4 - DEF_unk1
0xC0F080A8 - DEF_DEF_MODE (mask 0x11F, 0x100 always set)
0xC0F080AC - DEF_DEF_CTRL
0xC0F080B0 - DEF_YB_XB (mask 0x1FFF1FFF)
0xC0F080B4 - DEF_YN_XN
0xC0F080BC - DEF_YA_XA?
0xC0F080C0 - DEF_BUF_NUM
0xC0F080C4 - DEF_INTR_BE
0xC0F080C8 - DEF_INTR_AE (AdKizMerge)
0xC0F080D0 - DEF_INTR_NUM/DEF_INTR_EN?
0xC0F080D4 - DEF_HOSEI (mask 0x11)
0xC0F08100 - CCDSEL (0-1)
0xC0F08104 - DS_SEL (0-1)
0xC0F08108 - OBWB_ISEL (0-7)
0xC0F0810C - PROC24_ISEL (0-7)
0xC0F08110 - DPCME_ISEL (0-15)
0xC0F08114 - PACK32_ISEL (0-15)
0xC0F08120 - PACK16 Control register
0xC0F08124 - PACK16_MODE (mask 0x131)
From ProcessPathForFurikake (raw_twk):
-------x --xx----
1?? (0x100) = 16-bit output (? = don't care)
01? (0x020) = 14-bit output
001 (0x010) = 12-bit output
000 (0x000) = 10-bit output
0xC0F08130 - DEFM Control Register
0xC0F08134 - DEFM_unk1
0xC0F08138 - DEFM_MODE
0xC0F08140 - DEFM_INTR_NUM
0xC0F0814C - DEFM_GRADE
0xC0F08150 - DEFM_DAT_TH
0xC0F08154 - DEFM_INTR_CLR
0xC0F08158 - DEFM_INTR_EN
0xC0F0815C - DEFM_14_12_SEL
0xC0F08160 - DEFM_DAT_TH_14_12
0xC0F0816C - DEFM_X2MODE
0xC0F08180 - HIV Control Register
0xC0F08184 - HIV_V_SIZE
0xC0F08188 - HIV_H_SIZE
0xC0F0818C - HIV_POS_V_OFST
0xC0F08190 - HIV_POS_H_OFST
0xC0F08194 - HIV_unk1
0xC0F08198 - HIV_unk2
0xC0F0819C - HIV_POST_SETUP /* called SaturateOffset, seems black level, lowering it recovers extra highlights */
0xC0F081C0 - HIV_H_SWS_ENB
0xC0F08214 - HIV_PPR_EZ
0xC0F08218 - HIV_IN_SEL
0xC0F08220 - ADKIZ_unk1
0xC0F08224 - ADKIZ_THRESHOLD
0xC0F08234 - ADKIZ_TOTAL_SIZE
0xC0F08238 - ADKIZ_INTR_CLR
0xC0F0823C - ADKIZ_INTR_EN: interrupt enable (60D: 0x65)
0xC0F08240 - ADMERG_INTR_EN
0xC0F08244 - ADMERG_TOTAL_SIZE
0xC0F08248 - ADMERG_MergeDefectsCount
0xC0F08250 - ADMERG_2_IN_SE
0xC0F0825C - ADKIZ_THRESHOLD_14_12
0xC0F08260 - UNPACK24_DM_EN
0xC0F08264 - PACK32_DM_EN
0xC0F08268 - PACK32_MODE_H
0xC0F0826C - unk_MODE_H
0xC0F08270 - DEFC_X2MODE (0-1)
0xC0F08274 - DSUNPACK_DM_EN
0xC0F08278 - ADUNPACK_DM_EN (0-1)
0xC0F0827C - PACK16_CCD2_DM_EN
0xC0F08280 - SHAD_CBIT
0xC0F08284 - SHAD_C8MODE
0xC0F08288 - SHAD_C12MODE
0xC0F0828C - SHAD_RMODE (0-1)
0xC0F08290 - SHAD_COF_SEL
0xC0F082A0 - DARK_KZMK_SAV_A (0/1) (causes white or black screen)
0xC0F082A4 - DARK_KZMK_SAV_B (0/1) (no noticeable change)
0xC0F082A8 - SHAD_KZMK_SAV (0-1)
0xC0F082AC - TWOA_KZMK_SAV_A (0-1)
0xC0F082B0 - TWOA_KZMK_SAV_B (0-1)
0xC0F082B4 - DEFC_DET_MODE (0-1)
0xC0F082B8 - PACK16_DEFM_ON (0-1)
0xC0F082BC - PACK32_DEFM_ON
0xC0F082C4 - HIV_DEFMARK_CANCEL
0xC0F082D0 - PACK16_ISEL (0-15)
0xC0F082D4 - WDMAC32_ISEL (0-7)
0xC0F082D8 - WDMAC16_ISEL (0-1)
0xC0F082DC - OBINTG_ISEL (0-15)
0xC0F082E0 - AFFINE_ISEL (0-15)
0xC0F08390 - OBWB_ISEL2 (0-1)
0xC0F08394 - PROC24_ISEL2 (0-1)
0xC0F08398 - PACK32_ISEL2 (0-3)
0xC0F0839C - PACK16_ISEL2 (0-3)
0xC0F083A0 - TAIWAN_ISEL (0-3)
0xC0F08420 - HIV_BASE_OFST
0xC0F08428 - HIV_GAIN_DIV
0xC0F0842C - HIV_PATH
0xC0F08540 - RSHD_ENB
0xC0F085B0 - PACK32_ILIM
0xC0F085B4 - PACK16_ILIM (mask 0x3FFF)
Path Setup[]
These are dumps of the registers used for the video path and preprocessing configurations and the data that gets written to them. Registers are sorted by their address. a "<-" means, "see left" and a "*" marks registers that are written more than once per function call.
When neither a value nor a "<-" is in a field, this means the function does not write this register at all.
Horizontally you see the different live view/recording modes.
Example: See the first entry in the table below. This means: when having mode set to "Live view 1x zoom" (LVx1) the procedure "SetPreProcessingPath" will set 0xC0F08000 to 0x80000000. Same for all the other modes.
There is also a list with some addresses replaced with register names: http://pastebin.com/5irg7dWU
path 'PreProcessing' func 'Set*Path'
Mode 0x00 (LVx1) equals: 0x05 (LVx1_Ta10), 0x08 ((unknown)), 0x0E ((unknown)), 0x10 (RecStandby_x1), 0x12 (RecStandby_x1),
Mode 0x01 (RecStandby_x1_60fps) equals: 0x0B (Rec_720p), 0x11 (RecStandby_x1_60fps),
Mode 0x02 (LVx5) equals: 0x03 (LVx10), 0x06 (LVx5), 0x07 (LVx10),
Mode 0x04 (LV_VgaTele) equals: 0x0D (Rec_VgaTele),
Mode 0x09 (Rec_DZ_Crop_HD) equals: 0x0F (Rec_DZ_Crop_HD),
Mode 0x0A (Rec_HD) equals: 0x0C (Rec_Vga),
|
| 0x00 0x01 0x02 0x04 0x09 0x0A
| LVx1 RecStandby_x1_60fps LVx5 LV_VgaTele Rec_DZ_Crop_HD Rec_HD
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xC0F08000 | 0x80000000 <- <- <- <- <-
0xC0F08004 | 0x00000120 <- <- <- <- <-
0xC0F08008 | 0x00000000 <- <- <- <- <-
0xC0F0800C | 0x00000FFF <- <- <- <- <-
0xC0F08010 | 0x00000000 <- <- <- <- <-
0xC0F08014 | 0x00003FFF <- <- <- <- <-
0xC0F08018 | 0x00003FFF <- <- <- <- <-
0xC0F08020 | 0x80000000 <- <- <- <- <-
0xC0F08024 | 0x00001008 <- <- <- <- <-
0xC0F08028 | 0x00000000 <- <- <- <- <-
0xC0F0802C | 0x00000000 <- <- <- <- <-
0xC0F08030 | 0x00001000 <- <- <- <- <-
0xC0F08034 | 0x00001800 <- <- <- <- <-
0xC0F08038 | 0x00000800 <- <- <- <- <-
0xC0F08090 | 0x80000000 <- <- <- <- <-
0xC0F08094 | 0x00000030 <- <- <- <- <-
0xC0F080A0 | 0x80000000 <- <- <- <- <-
0xC0F080A4 | 0x00000000 <- <- <- <- <-
0xC0F080A8 | 0x00000103 <- <- <- <- <-
0xC0F080AC | 0x00000000 <- <- <- <- <-
0xC0F080B0 | 0x049D075F 0x02CF075F 0x045109D7 0x026F0397 0x0417079F 0x049D075F
0xC0F080B4 | 0x00000000 <- <- <- <- <-
0xC0F080BC | 0x00000000 <- <- <- <- <-
0xC0F080D0 | 0x00000000 <- <- <- <- <-
0xC0F080D4 | 0x00000011 <- <- <- <- <-
0xC0F08100 | 0x00000000 <- <- <- <- <-
0xC0F08108 | 0x00000003 <- <- <- <- <-
0xC0F0810C | 0x0000000E <- <- <-
0xC0F08114 | 0x0000000B 0x00000005 0x0000000B <- <- 0x00000005
0xC0F08130 | 0x80000000 <- <- <- <- <-
0xC0F08134 | 0x00000001 <- <- <- <- <-
0xC0F08138 | 0x00000010 <- <- <- <- <-
0xC0F08140 | 0x00000000 <- <- <- <- <-
0xC0F0814C | 0x0000000E <- <- <- <- <-
0xC0F08150 | 0x00000FFF <- <- <- <- <-
0xC0F08154 | 0x00000008 <- <- <- <- <-
0xC0F08158 | 0x00000000 <- <- <- <- <-
0xC0F0815C | 0x00000002 <- <- <- <- <-
0xC0F08160 | 0x00003FFF <- <- <- <- <-
0xC0F08180 | *0x80000000 * <- * <- * <- * <- * <-
0xC0F08184 | 0x0000049D 0x000002CF 0x00000451 0x0000026F 0x00000417 0x0000049D
0xC0F08188 | 0x0000075F <- 0x000009D7 0x00000397 0x0000079F 0x0000075F
0xC0F0818C | 0x00000000 <- <- <- <- <-
0xC0F08190 | 0x00000000 <- <- <- <- <-
0xC0F08194 | 0x0000075F <- 0x000009D7 0x00000397 0x0000079F 0x0000075F
0xC0F08198 | 0x0000075F <- 0x000009D7 0x00000397 0x0000079F 0x0000075F
0xC0F0819C | 0x00000800 <- <- <- <- <-
0xC0F081A4 | 0x00000001 <- <- <- <- <-
0xC0F081A8 | 0x00000001 <- <- <- <- <-
0xC0F081AC | 0x00000000 <- <- <- <- <-
0xC0F081B0 | 0x00000000 <- <- <- <- <-
0xC0F081B4 | 0x00000000 <- <- <- <- <-
0xC0F081C4 | 0x00000001 <- <- <- <- <-
0xC0F081C8 | 0x00000000 <- <- <- <- <-
0xC0F081CC | 0x00000000 <- <- <- <- <-
0xC0F081D0 | 0x00000000 <- <- <- <- <-
0xC0F081D4 | 0x00000000 <- <- <- <- <-
0xC0F081D8 | 0x00000000 <- <- <- <- <-
0xC0F081DC | 0x00000000 <- <- <- <- <-
0xC0F081E0 | 0x00000001 <- <- <- <- <-
0xC0F081E4 | 0x00000000 <- <- <- <- <-
0xC0F081E8 | 0x00000000 <- <- <- <- <-
0xC0F081EC | 0x00000000 <- <- <- <- <-
0xC0F081F0 | 0x00000000 <- <- <- <- <-
0xC0F081F4 | 0x00000000 <- <- <- <- <-
0xC0F08214 | 0x00000000 <- <- <- <- <-
0xC0F08218 | 0x0000000A <- <- <- <- <-
0xC0F08264 | *0x00000000 * <- * <- * <- * <- * <-
0xC0F08268 | 0x00000000 <- <- <- <- <-
0xC0F0826C | 0x00000000 <- <- <- <- <-
0xC0F08270 | 0x00000000 <- <- <- <- <-
0xC0F08280 | 0x00000000 <- <- <- <- <-
0xC0F08284 | 0x00000000 <- <- <- <- <-
0xC0F08288 | 0x00000000 <- <- <- <- <-
0xC0F0828C | 0x00000001 <- <- <- <- <-
0xC0F08290 | 0x00000000 <- <- <- <- <-
0xC0F082A0 | 0x00000000 <- <- <- <- <-
0xC0F082A4 | 0x00000001 <- <- <- <- <-
0xC0F082A8 | 0x00000001 <- <- <- <- <-
0xC0F082B4 | 0x00000001 <- <- <- <- <-
0xC0F082C4 | 0x00000001 <- <- <- <- <-
0xC0F082D4 | 0x00000000 <- <- <- <- <-
0xC0F082DC | 0x00000004 <- <- <- <- <-
0xC0F082E0 | 0x00000005 <- <- <- <- <-
0xC0F08390 | 0x00000000 <- <- <- <- <-
0xC0F08394 | 0x00000000 <- 0x00000002 <- 0x00000000 <-
0xC0F08398 | 0x00000000 <- <- <- <- <-
0xC0F083B0 | 0x00000000 <- <- <- <- <-
0xC0F083B4 | 0x00000004 <- <- <- <- <-
0xC0F083B8 | 0x00000001 <- <- <- <- <-
0xC0F083BC | 0x00000000 <- <- <- <- <-
0xC0F083C0 | 0x00000001 <- <- <- <- <-
0xC0F083E8 | 0x00000000 <- <- <- <- <-
0xC0F083EC | 0x00000000 <- <- <- <- <-
0xC0F083F0 | 0x1FFF0000 <- <- <- <- <-
0xC0F083F4 | 0x00000000 <- <- <- <- <-
0xC0F083F8 | 0x00000000 <- <- <- <- <-
0xC0F083FC | 0x00000000 <- <- <- <- <-
0xC0F08404 | 0x00000000 <- <- <- <- <-
0xC0F08420 | 0x00000600 <- <- <- <- <-
0xC0F08428 | 0x00000111 <- <- <- <- <-
0xC0F0842C | 0x00000000 <- <- <- <- <-
0xC0F08430 | 0x00000000 <- <- <- <- <-
0xC0F08510 | 0x00000000 <- <-
0xC0F08514 | 0x00000000 <- <-
0xC0F08518 | 0x045109D7 0x026F0397 0x0417079F
0xC0F0851C | 0x00DC02E0 0x00490108 <-
0xC0F08520 | 0x039006F8 0x02370000 <-
0xC0F08540 | 0x80000000 <- <- <- <- <-
0xC0F08544 | 0x00000116 <- <- <- <- <-
0xC0F08548 | 0x049D075F 0x02CF075F 0x045109D7 0x026F0397 0x0417079F 0x049D075F
0xC0F0854C | 0x00000000 <- <- <- <- <-
0xC0F08550 | 0x1FFF1FFF <- <- <- <- <-
0xC0F08554 | 0x1FFF1FFF <- <- <- <- <-
0xC0F08558 | 0x01010101 <- <- <- <- <-
0xC0F0855C | 0x00000000 <- <- <- <- <-
0xC0F08560 | 0x00000800 <- <- <- <- <-
0xC0F08564 | 0x00000000 <- <- <- <- <-
0xC0F08568 | 0x0000003F <- <- <- <- <-
0xC0F0856C | 0x00000000 <- <- <- <- <-
0xC0F08570 | 0x00000800 <- <- <- <- <-
0xC0F08574 | 0x00000000 <- <- <- <- <-
0xC0F08580 | 0x00000001 <- <- <- <- <-
0xC0F0858C | 0x00000000 <- <- <- <- <-
0xC0F08590 | 0x00000000 <- <- <- <- <-
0xC0F08594 | 0x00000000 <- <- <- <- <-
0xC0F08650 | 0x00000000 <- <- <- <- <-
0xC0F08654 | 0x00000001 <- <- <- <- <-
path 'PreProcessing' func 'Start*Path'
Mode 0x00 (LVx1) equals: 0x05 (LVx1_Ta10), 0x08 ((unknown)), 0x0E ((unknown)), 0x10 (RecStandby_x1), 0x12 (RecStandby_x1),
Mode 0x01 (RecStandby_x1_60fps) equals: 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x11 (RecStandby_x1_60fps),
Mode 0x02 (LVx5) equals: 0x06 (LVx5),
Mode 0x03 (LVx10) equals: 0x04 (LV_VgaTele), 0x07 (LVx10), 0x09 (Rec_DZ_Crop_HD), 0x0D (Rec_VgaTele), 0x0F (Rec_DZ_Crop_HD),
|
| 0x00 0x01 0x02 0x03
| LVx1 RecStandby_x1_60fps LVx5 LVx10
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xC0F08000 | 0x00000001 <- <- <-
0xC0F08020 | 0x00000001 <- <- <-
0xC0F08090 | 0x00000001 <- <- <-
0xC0F080A0 | 0x00000001 <- <- <-
0xC0F08130 | 0x00000001 <- <- <-
0xC0F08180 | 0x00000001 <- <- <-
0xC0F08208 | *0x00000010 * <-
0xC0F083B0 | 0x00000001 <- <- <-
0xC0F08510 | 0x00000001 <-
0xC0F08540 | 0x00000001 <- <- <-
path 'PreProcessing' func 'Stop*Path'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x05 (LVx1_Ta10), 0x08 ((unknown)), 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x0E ((unknown)), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
Mode 0x02 (LVx5) equals: 0x03 (LVx10), 0x04 (LV_VgaTele), 0x06 (LVx5), 0x07 (LVx10), 0x09 (Rec_DZ_Crop_HD), 0x0D (Rec_VgaTele), 0x0F (Rec_DZ_Crop_HD),
|
| 0x00 0x02
| LVx1 LVx5
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xC0F08000 | 0x80000000 <-
0xC0F08020 | 0x80000000 <-
0xC0F08090 | 0x80000000 <-
0xC0F080A0 | 0x80000000 <-
0xC0F08130 | 0x80000000 <-
0xC0F08180 | 0x80000000 <-
0xC0F083B0 | 0x00000000 <-
0xC0F08510 | 0x80000000
0xC0F08540 | 0x80000000 <-
path 'PreProcessing' func 'Start*YuvPass'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x02 (LVx5), 0x03 (LVx10), 0x04 (LV_VgaTele), 0x05 (LVx1_Ta10), 0x06 (LVx5), 0x07 (LVx10), 0x08 ((unknown)), 0x09 (Rec_DZ_Crop_HD), 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x0D (Rec_VgaTele), 0x0E ((unknown)), 0x0F (Rec_DZ_Crop_HD), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
|
| 0x00
| LVx1
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
path 'PreProcessing' func '(unused)'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x02 (LVx5), 0x03 (LVx10), 0x04 (LV_VgaTele), 0x05 (LVx1_Ta10), 0x06 (LVx5), 0x07 (LVx10), 0x08 ((unknown)), 0x09 (Rec_DZ_Crop_HD), 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x0D (Rec_VgaTele), 0x0E ((unknown)), 0x0F (Rec_DZ_Crop_HD), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
|
| 0x00
| LVx1
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
path 'VRAM' func 'Set*Path'
Mode 0x01 (RecStandby_x1_60fps) equals: 0x0B (Rec_720p), 0x11 (RecStandby_x1_60fps),
Mode 0x02 (LVx5) equals: 0x06 (LVx5),
Mode 0x03 (LVx10) equals: 0x07 (LVx10),
Mode 0x08 ((unknown)) equals: 0x0E ((unknown)),
Mode 0x09 (Rec_DZ_Crop_HD) equals: 0x0F (Rec_DZ_Crop_HD),
Mode 0x0C (Rec_Vga) equals: 0x10 (RecStandby_x1), 0x12 (RecStandby_x1),
|
| 0x00 0x01 0x02 0x03 0x04 0x05 0x08 0x09 0x0A 0x0C 0x0D
| LVx1 RecStandby_x1_60fps LVx5 LVx10 LV_VgaTele LVx1_Ta10 (unknown) Rec_DZ_Crop_HD Rec_HD Rec_Vga Rec_VgaTele
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xC0F0430C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F04310 | 0x01DF05A0 <- <- <- 0x01DF0500 0x01DF05A0 0x019305A0 0x01DF0500 0x01DF05A0 <- 0x01DF0500
0xC0F04314 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F04318 | 0x00000000 <- <- <- 0x000000A0 0x00000000 <- <- <- <- 0x000000A0
0xC0F0431C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F04320 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F04324 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F04328 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F04F10 | 0x00000001 <- <- <- <- <- <- <- <- <-
0xC0F0D000 | 0x80000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D004 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D008 | 0x77772222 <- <- <- 0xDDDD8888 0x77772222 <- <- <- <- 0xDDDD8888
0xC0F0D00C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D010 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D014 | 0x049D0760 0x02CF0760 0x02B30418 <- 0x01ED0290 0x049D0760 <- 0x041707A0 0x049D0760 <- 0x01ED0290
0xC0F0D018 | 0x000007AF 0x0000079B 0x0000046F <- 0x000002E7 0x000007AF <- 0x000007EB 0x0000079B <- 0x000002E7
0xC0F0D01C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D020 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D024 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D028 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D02C | *0x00000000 * <- * <- * <- * <- * <- * <- * <- * <- * <- * <-
0xC0F0D030 | 0x00000010 <- <- <- 0x00000040 0x00000010 <- <- <- <- 0x00000040
0xC0F0D038 | 0x00000020 <- <- <- <- <- <- <- <- <- <-
0xC0F0D03C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D040 | *0x00000000 * <- * <- * <- * <- * <- * <- * <- * <- * <- * <-
0xC0F0D044 | *0x00000000 * <- * <- * <- * <- * <- * <- * <- * <- * <- * <-
0xC0F0D048 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D04C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D050 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D054 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D058 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D05C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D060 | 0x00000000 <- <-
0xC0F0D064 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D068 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D06C | 0x00000000 <- <- <- <- <- <- <-
0xC0F0D070 | 0x00000001 <- <- <- <- <- <- <- <- <- <-
0xC0F0D074 | 0x00000113 <- <- <- <- <- <- <- <- <- <-
0xC0F0D078 | 0x00000001 <- <- <- <- <- <- <- <- <- <-
0xC0F0D07C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D080 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D084 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D088 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D094 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D098 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D09C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D0A4 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D0A8 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0D0AC | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F11004 | 0x00000000 <- <- <- <- <- <- <- <- <-
0xC0F1100C | 0x00000000
0xC0F11044 | 0x00000000 <- <- <- <- <- <- <- <- <-
0xC0F1108C | 0x00000004 <- <- <- <- <- <- <- <- <-
0xC0F11094 | 0x00000005
0xC0F110C4 | 0x00000001 <- 0x0000000A <- 0x00000001 0x00000003 0x0000000A <- 0x00000001 <- <-
0xC0F11100 | 0x00000009 <- <- <- <- <- <- <- <- <- <-
0xC0F11104 | 0x00000001 <- <- <-
0xC0F11108 | 0x00000005 <- <- <- <- <- <- <- <- <- <-
0xC0F11144 | 0x00000007 <- <- <- <- <- <- <- <- <- <-
0xC0F11170 | 0x00000001 <- <- <- <- <- <- <- <- <- <-
0xC0F111C0 | 0x00000001 <- <- <- <- <- <- <- <- <- <-
0xC0F111C4 | 0x00000001 <- 0x00000000 <- <- 0x00000001 <- 0x00000000 0x00000001 <- 0x00000000
0xC0F111C8 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F11240 | 0x00000001 <- <- <-
0xC0F11244 | 0x00000000 <- <- <-
0xC0F11248 | 0x00000000 0x00000003 <- <-
0xC0F1124C | 0x02AF0407 <- 0x03CB06B7 <-
0xC0F11250 | 0x00000000 0x00AC0102 0x00020004 <-
0xC0F11254 | 0x02AF0407 0x02040307 0x03C906B7 <-
0xC0F11258 | 0x00000000 <- <- <-
0xC0F1125C | 0x00000000 <- <- <-
0xC0F11260 | 0x00000000 <- <- <-
0xC0F11264 | 0x00000000 <- <- <-
0xC0F112C0 | 0x00000001 <- <- <- <- <- <- <- <- <- <-
0xC0F112C4 | 0x00011010 <- <- 0x00010011 0x00010100 0x00011010 <- 0x00010100 0x00011010 <- 0x00010100
0xC0F112C8 | 0x0007242B 0x002A0607 0x00081E2B 0x00042B3C 0x00000000 0x0007242B <- 0x00000000 0x002A0607 <- 0x00000000
0xC0F112CC | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F112D0 | 0x000002CF <- <- <- 0x00000000 0x000002CF <- 0x00000000 0x000002CF <- 0x00000000
0xC0F112D4 | 0x0477035C 0x029F0348 0x02AF0408 0x01DF0FFF 0x00000000 0x0477035C 0x03C7035C 0x00000000 0x045F0348 <- 0x00000000
0xC0F112D8 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F112DC | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F11300 | 0x00000001 <- <- <- <- <- <- <- <- <- <-
0xC0F11304 | 0x00000010 <- <- 0x00000011 0x00000000 0x00000010 <- 0x00000000 0x00000010 <- 0x00000000
0xC0F11308 | 0x0002788F 0x00330507 0x00081E2B 0x00042B3C 0x00000000 0x0002788F 0x00026579 0x00000000 0x002A0607 <- 0x00000000
0xC0F1130C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F11310 | 0x03BF0000 0x01DF0000 <- <- 0x00000000 0x03BF0000 0x03270000 0x00000000 0x03BF0000 <- 0x00000000
0xC0F11314 | 0x047702CF 0x029F02CF 0x02AF02CF 0x0FFF0205 0x00000000 0x047702CF 0x03C702CF 0x00000000 0x045F02CF <- 0x00000000
0xC0F11318 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F1131C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F1133C | 0x000001BB <- <- 0x000002EE 0x0000008A 0x000001BB <- 0x0000008A 0x000001BB <- 0x0000008A
0xC0F11440 | 0x00000001 <- <- <- <- <- <- <- <- <- <-
0xC0F11444 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F11448 | 0x00001000 <- <- <- <- <- <- <- <- <- <-
0xC0F1144C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F11450 | 0x01DF02CF <- <- <- 0x01DF027F 0x01DF02CF 0x019302CF 0x01DF027F 0x01DF02CF <- 0x01DF027F
0xC0F11454 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F11580 | 0x00000001 <- <- <- <- <- <- <- <- <- <-
0xC0F11584 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F11588 | 0x00000001 0x00000000 <- <- <- 0x00000001 <- 0x00000000 0x00000001 <- 0x00000000
0xC0F1158C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F11590 | 0x01DF02CF <- <- <- 0x03BF027F 0x01DF02CF 0x019302CF 0x03BF027F 0x01DF02CF <- 0x03BF027F
0xC0F11594 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F15000 | 0x00000005
0xC0F15004 | 0x00000000
0xC0F1500C | 0x00000000
0xC0F1501C | 0x00000000
0xC0F15040 | 0x80000000
0xC0F15044 | 0x00010000
0xC0F15048 | 0x00000000
0xC0F1504C | 0x047706B7
0xC0F15050 | 0x00000000
0xC0F15054 | 0x00000000
0xC0F15058 | 0x00000000
0xC0F15060 | 0x80000000
0xC0F15064 | 0x00010000
0xC0F15068 | 0x00000000
0xC0F1506C | 0x047706B7
0xC0F15070 | 0x00000000
0xC0F15074 | 0x00000000
0xC0F15078 | 0x00000000
0xC0F150A0 | 0x80000000
0xC0F150A4 | 0x07001071
0xC0F150A8 | 0x00000000
0xC0F150AC | 0x00000000
0xC0F150B0 | 0x00000000
0xC0F150B4 | 0x00000026
0xC0F15100 | 0x80000000
0xC0F15104 | 0x00040000
0xC0F15108 | 0x00000000
0xC0F1510C | 0x047706B7
0xC0F15110 | 0x00000000
0xC0F15114 | 0x00000000
0xC0F15118 | 0x00000000
0xC0F25000 | 0x00000001 <- <- <- <- <- <- <- <- <- <-
0xC0F25004 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F25008 | 0x00000001 <- <- <- <- <- <- <- <- <- <-
0xC0F2500C | 0x000006B7 0x0000068F 0x00000407 <- 0x0000027F 0x000006B7 <- 0x000006BF 0x0000068F <- 0x0000027F
0xC0F25010 | 0x00000001 <- <- <- <- <- <- <- <- <- <-
0xC0F25014 | 0x00000001 <- <- <- <- <- 0x00000000 <- 0x00000001 <- <-
0xC0F2501C | 0x00000000 0x0000000F 0x00000000 <- <- <- <- <- <- 0x0000000F 0x00000000
0xC0F25024 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F25028 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F25034 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F25038 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F25044 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F25048 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F2504C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F25050 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F25054 | 0x000006B7 0x0000068F 0x00000407 <- 0x0000027F 0x000006B7 <- 0x000006BF 0x0000068F <- 0x0000027F
0xC0F25058 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F2505C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
path 'VRAM' func 'Start*Path'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x04 (LV_VgaTele), 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x0D (Rec_VgaTele), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
Mode 0x02 (LVx5) equals: 0x03 (LVx10), 0x06 (LVx5), 0x07 (LVx10), 0x08 ((unknown)), 0x09 (Rec_DZ_Crop_HD), 0x0E ((unknown)), 0x0F (Rec_DZ_Crop_HD),
|
| 0x00 0x02 0x05
| LVx1 LVx5 LVx1_Ta10
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xC0F03048 | *0x00000002 * <- * <-
0xC0F03050 | *0x00000002 * <- * <-
0xC0F0D000 | 0x00000001 <- <-
0xC0F11004 | 0x00000001 <-
0xC0F1100C | 0x00000001
0xC0F11044 | 0x00000001 <- <-
0xC0F11064 | 0x00000001 <- <-
0xC0F111C0 | 0x00000000 <- <-
0xC0F11240 | 0x00000000
0xC0F11244 | 0x00000001
0xC0F112C0 | 0x00000000 <- <-
0xC0F11300 | 0x00000000 <- <-
0xC0F11440 | 0x00000000 <- <-
0xC0F11444 | 0x00000001 <- <-
0xC0F11580 | 0x00000000 <- <-
0xC0F11584 | 0x00000001 <- <-
path 'VRAM' func 'Stop*Path'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x04 (LV_VgaTele), 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x0D (Rec_VgaTele), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
Mode 0x02 (LVx5) equals: 0x03 (LVx10), 0x06 (LVx5), 0x07 (LVx10), 0x08 ((unknown)), 0x09 (Rec_DZ_Crop_HD), 0x0E ((unknown)), 0x0F (Rec_DZ_Crop_HD),
|
| 0x00 0x02 0x05
| LVx1 LVx5 LVx1_Ta10
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xC0F0D000 | 0x80000000 <- <-
0xC0F11004 | 0x00000000 <-
0xC0F1100C | 0x00000000
0xC0F11044 | 0x00000000 <- <-
0xC0F111C0 | 0x00000001 <- <-
0xC0F11240 | 0x00000001
0xC0F11244 | 0x00000000
0xC0F112C0 | 0x00000001 <- <-
0xC0F11300 | 0x00000001 <- <-
0xC0F11440 | 0x00000001 <- <-
0xC0F11444 | 0x00000000 <- <-
0xC0F11580 | 0x00000001 <- <-
0xC0F11584 | 0x00000000 <- <-
path 'VRAM' func 'Start*YuvPass'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x02 (LVx5), 0x03 (LVx10), 0x04 (LV_VgaTele), 0x05 (LVx1_Ta10), 0x06 (LVx5), 0x07 (LVx10), 0x08 ((unknown)), 0x09 (Rec_DZ_Crop_HD), 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x0D (Rec_VgaTele), 0x0E ((unknown)), 0x0F (Rec_DZ_Crop_HD), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
|
| 0x00
| LVx1
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
path 'VRAM' func '(unused)'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x02 (LVx5), 0x03 (LVx10), 0x04 (LV_VgaTele), 0x05 (LVx1_Ta10), 0x06 (LVx5), 0x07 (LVx10), 0x08 ((unknown)), 0x09 (Rec_DZ_Crop_HD), 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x0D (Rec_VgaTele), 0x0E ((unknown)), 0x0F (Rec_DZ_Crop_HD), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
|
| 0x00
| LVx1
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
path 'YUV' func 'Set*Path'
Mode 0x01 (RecStandby_x1_60fps) equals: 0x11 (RecStandby_x1_60fps),
Mode 0x02 (LVx5) equals: 0x03 (LVx10), 0x06 (LVx5), 0x07 (LVx10),
Mode 0x08 ((unknown)) equals: 0x0E ((unknown)),
Mode 0x09 (Rec_DZ_Crop_HD) equals: 0x0F (Rec_DZ_Crop_HD),
Mode 0x10 (RecStandby_x1) equals: 0x12 (RecStandby_x1),
|
| 0x00 0x01 0x02 0x04 0x05 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x10
| LVx1 RecStandby_x1_60fps LVx5 LV_VgaTele LVx1_Ta10 (unknown) Rec_DZ_Crop_HD Rec_HD Rec_720p Rec_Vga Rec_VgaTele RecStandby_x1
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xC0F0420C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F04210 | 0x02BF0840 0x02A70800 <- 0x01DF0500 0x03CB0D70 0x01DF0500 0x03B70D20 0x02370A00 0x01DF0500 <- 0x02BF0840
0xC0F04214 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F04218 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F0421C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F04220 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F04224 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F04228 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F110C0 | 0x00000007 <- <- <- <- <-
0xC0F11104 | 0x00000001 <- <- <-
0xC0F11110 | 0x00000001 <- <- <- 0x00000008 <- 0x00000001
0xC0F11114 | 0x0000000B <- <- <- <- <-
0xC0F11118 | 0x00000004 <- <- <- <- <-
0xC0F11128 | 0x0000000A
0xC0F11130 | 0x0000000D <- <- <- 0x00000001 <- 0x00000008 0x0000000B 0x0000000D 0x00000008 0x0000000D
0xC0F11180 | 0x00000001 <- <- <- <- <-
0xC0F11184 | 0x00000000 <- <- <- 0x00000001 0x00000000
0xC0F11188 | 0x00000000 <- <- <- <- <-
0xC0F11240 | 0x00000001 <- <- <-
0xC0F11244 | 0x00000000 <- <- <-
0xC0F11248 | 0x00000003 <- <- 0x00000000
0xC0F1124C | 0x045F068F 0x029F068F 0x045F068F 0x01DF027F
0xC0F11250 | 0x00580000 0x00340000 0x0000005E 0x00000000
0xC0F11254 | 0x040F068F 0x026B068F 0x045F0631 0x01DF027F
0xC0F11258 | 0x00000000 <- <- <-
0xC0F1125C | 0x00000000 <- <- <-
0xC0F11260 | 0x00000000 <- <- <-
0xC0F11264 | 0x00000000 <- <- <-
0xC0F11500 | 0x00000001 <- <- <- <- <- <-
0xC0F11504 | 0x00000000 <- <- <- <- <- <-
0xC0F11508 | 0x00000000 <- <- 0x80000000 0x00000000 <- <-
0xC0F1150C | 0x008400D7 0x00400069 0x00800081 0x00000000 0x00100015 0x01400175 0x00160023
0xC0F11510 | 0x000703E1 0x00050200 0x00060200 0x00000000 0x00030200 0x00080333 0x000402E9
0xC0F11514 | 0x00000000 <- <- <- <- <- <-
0xC0F11518 | 0x0000041F 0x000003FF <- 0x0000027F 0x000004FF <- 0x0000041F
0xC0F1151C | 0x047706B7 0x029F068F 0x02AF0407 0x01DF027F 0x0237068F 0x045F05D3 0x045F068F
0xC0F11520 | 0x00000000 <- <- <- <- <- <-
0xC0F11524 | 0x00000000 <- <- <- <- <- <-
0xC0F11540 | 0x00000001 <- <- <- <- <-
0xC0F11544 | 0x00000000 <- <- <- <- <-
0xC0F11548 | 0x00000000 0x00000001 0x00000000 0x80000000 0x00000000 <-
0xC0F1154C | 0x0008000D 0x00540055 0x00550056 0x00000000 0x00060007 0x00160023
0xC0F11550 | 0x00020200 0x00060303 <- 0x00000000 0x000202AB 0x000402E9
0xC0F11554 | 0x00000000 <- <- <- <- <-
0xC0F11558 | 0x000002BF 0x000002A7 <- 0x000001DF 0x000003BF 0x000002BF
0xC0F1155C | 0x0477041F 0x029F03FF 0x02AF03FF 0x01DF027F 0x045F04FF 0x045F041F
0xC0F11560 | 0x00000000 <- <- <- <- <-
0xC0F11564 | 0x00000000 <- <- <- <- <-
0xC0F116A0 | 0x00000001 <- <- <- <- <-
0xC0F116A4 | 0x00000000 <- <- <- <- <-
0xC0F116A8 | 0x00000000 <- <- <- 0x00000001 0x00000000
0xC0F116AC | 0x00000000 <- <- <- <- <-
0xC0F116B0 | 0x02BF041F 0x02A703FF <- 0x01DF027F <- 0x02BF041F
0xC0F116B4 | 0x00000000 <- <- <- <- <-
0xC0F2600C | 0x00000000
0xC0F26010 | 0x027F0276
0xC0F26014 | 0x00000000
0xC0F26018 | 0x00000000
0xC0F2601C | 0x00000000
0xC0F26020 | 0x00000000
0xC0F26024 | 0x00000000
0xC0F26028 | 0x00000000
0xC0F2A000 | 0x80000000
0xC0F2A00C | 0x00000001
0xC0F2A010 | 0x00000001
0xC0F2A014 | 0x00000000
0xC0F2A018 | 0x01DF04FE
0xC0F2A01C | 0x00000000
0xC0F2A020 | 0x00010001
0xC0F2A024 | 0x00000000
0xC0F2A028 | 0x00000000
0xC0F2A02C | 0x01DF04FE
0xC0F2C000 | 0x00000002 <- <- <- <- <- <- <- <- <- <-
0xC0F2C004 | 0x80000000 <- <- <- <- <- <- <- <- <- <-
0xC0F2C008 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F2C00C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F2C010 | 0x00000001 <- <- <- <- <- <- <- <- <- <-
0xC0F2C014 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F2C018 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F2C01C | 0x02BF041F 0x02A703FF <- 0x01DF027F 0x03CB06B7 0x01DF027F 0x03B7068F 0x023704FF 0x01DF027F <- 0x02BF041F
0xC0F2C020 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F2C024 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F2C028 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F2C02C | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F2C030 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
0xC0F2C034 | 0x00000000 <- <- <- <- <- <- <- <- <- <-
path 'YUV' func 'Start*Path'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x02 (LVx5), 0x03 (LVx10), 0x04 (LV_VgaTele), 0x06 (LVx5), 0x07 (LVx10), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
Mode 0x08 ((unknown)) equals: 0x09 (Rec_DZ_Crop_HD), 0x0E ((unknown)), 0x0F (Rec_DZ_Crop_HD),
Mode 0x0A (Rec_HD) equals: 0x0D (Rec_VgaTele),
|
| 0x00 0x05 0x08 0x0A 0x0B 0x0C
| LVx1 LVx1_Ta10 (unknown) Rec_HD Rec_720p Rec_Vga
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xC0F03074 | *0x00000002 * <-
0xC0F030C0 | *0x00000002 * <-
0xC0F11180 | 0x00000000 <-
0xC0F11240 | 0x00000000 <- <-
0xC0F11244 | 0x00000001 <- <-
0xC0F11500 | 0x00000000 <- <-
0xC0F11504 | 0x00000001 <- <-
0xC0F11540 | 0x00000000 <-
0xC0F11544 | 0x00000001 <-
0xC0F116A0 | 0x00000000 <-
0xC0F116A4 | 0x00000001 <-
0xC0F2A000 | 0x00000001
0xC0F2C004 | 0x00000001 <- <- <- <-
0xC0F2C008 | 0x00000001 <- <- <- <-
0xC0F2C00C | 0x00000001 <- <- <- <-
path 'YUV' func 'Stop*Path'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x02 (LVx5), 0x03 (LVx10), 0x04 (LV_VgaTele), 0x06 (LVx5), 0x07 (LVx10), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
Mode 0x08 ((unknown)) equals: 0x0E ((unknown)),
Mode 0x09 (Rec_DZ_Crop_HD) equals: 0x0F (Rec_DZ_Crop_HD),
|
| 0x00 0x05 0x08 0x09 0x0A 0x0B 0x0C 0x0D
| LVx1 LVx1_Ta10 (unknown) Rec_DZ_Crop_HD Rec_HD Rec_720p Rec_Vga Rec_VgaTele
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xC0F11180 | 0x00000001 <-
0xC0F11240 | 0x00000001 <- <- <-
0xC0F11244 | 0x00000000 <- <- <-
0xC0F11500 | 0x00000001 <- <-
0xC0F11504 | 0x00000000 <- <-
0xC0F11540 | 0x00000001 <-
0xC0F11544 | 0x00000000 <-
0xC0F116A0 | 0x00000001 <-
0xC0F116A4 | 0x00000000 <-
0xC0F2A000 | 0x80000000
0xC0F2C004 | 0x80000000 <- * <- <- <- <- * <-
0xC0F2C008 | 0x00000000 <- <- <-
0xC0F2C00C | 0x00000000 <- <- <-
path 'YUV' func 'Start*YuvPass'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x02 (LVx5), 0x03 (LVx10), 0x04 (LV_VgaTele), 0x05 (LVx1_Ta10), 0x06 (LVx5), 0x07 (LVx10), 0x08 ((unknown)), 0x09 (Rec_DZ_Crop_HD), 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x0D (Rec_VgaTele), 0x0E ((unknown)), 0x0F (Rec_DZ_Crop_HD), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
|
| 0x00
| LVx1
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
path 'YUV' func '(unused)'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x02 (LVx5), 0x03 (LVx10), 0x04 (LV_VgaTele), 0x05 (LVx1_Ta10), 0x06 (LVx5), 0x07 (LVx10), 0x08 ((unknown)), 0x09 (Rec_DZ_Crop_HD), 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x0D (Rec_VgaTele), 0x0E ((unknown)), 0x0F (Rec_DZ_Crop_HD), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
|
| 0x00
| LVx1
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
path 'Quark' func 'Set*Path'
Mode 0x00 (LVx1) equals: 0x02 (LVx5), 0x03 (LVx10), 0x06 (LVx5), 0x07 (LVx10), 0x10 (RecStandby_x1), 0x12 (RecStandby_x1),
Mode 0x01 (RecStandby_x1_60fps) equals: 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x11 (RecStandby_x1_60fps),
Mode 0x08 ((unknown)) equals: 0x0E ((unknown)),
Mode 0x09 (Rec_DZ_Crop_HD) equals: 0x0D (Rec_VgaTele), 0x0F (Rec_DZ_Crop_HD),
|
| 0x00 0x01 0x04 0x05 0x08 0x09
| LVx1 RecStandby_x1_60fps LV_VgaTele LVx1_Ta10 (unknown) Rec_DZ_Crop_HD
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xC0F0450C | 0x00000000 <-
0xC0F04510 | 0x027F05A0 0x010F02D0
0xC0F04514 | 0x00000000 <-
0xC0F04518 | 0x00000000 <-
0xC0F0451C | 0x00000000 <-
0xC0F04520 | 0x00000000 <-
0xC0F04524 | 0x00000000 <-
0xC0F04528 | 0x00000000 <-
0xC0F11004 | 0x00000000
0xC0F1100C | 0x00000000
0xC0F1108C | 0x00000003
0xC0F11094 | 0x00000003
0xC0F1110C | 0x00000001 0x00000003
0xC0F11128 | 0x0000000A <- <- <-
0xC0F11140 | 0x0000000A <-
0xC0F11340 | 0x00000001 <-
0xC0F11344 | 0x00011010 <-
0xC0F11348 | 0x000A182B <-
0xC0F1134C | 0x00000000 <-
0xC0F11350 | 0x000003BF 0x000001DF
0xC0F11354 | 0x027F06B8 0x021B06B8
0xC0F11358 | 0x00000000 <-
0xC0F1135C | 0x00000000 <-
0xC0F11380 | 0x00000001 <-
0xC0F11388 | 0x0000508F 0x00000509
0xC0F1138C | 0x00000000 <-
0xC0F11394 | 0x047706B7 0x03CB06B7
0xC0F1139C | 0x00000000 <-
0xC0F113BC | 0x00000001 <-
0xC0F11400 | 0x00000001 <-
0xC0F11404 | 0x00000000 <-
0xC0F11408 | 0x00000000 <-
0xC0F1140C | 0x00000000 <-
0xC0F11410 | 0x027F03BF 0x010F01DF
0xC0F11414 | 0x00000000 <-
0xC0F2600C | 0x00000000 <-
0xC0F26010 | 0x00FF00FC 0x027F0276
0xC0F26014 | 0x00000000 <-
0xC0F26018 | 0x00000000 <-
0xC0F2601C | 0x00000000 <-
0xC0F26020 | 0x00000000 <-
0xC0F26024 | 0x00000000 <-
0xC0F26028 | 0x00000000 <-
0xC0F2610C | 0x00000000 <-
0xC0F26110 | 0x00FF00FC 0x01DF01A4
0xC0F26114 | 0x00000000 <-
0xC0F26118 | 0x00000000 <-
0xC0F2611C | 0x00000000 <-
0xC0F26120 | 0x00000000 <-
0xC0F26124 | 0x00000000 <-
0xC0F26128 | 0x00000000 <-
0xC0F2A000 | 0x80000000 <- <- <-
0xC0F2A00C | 0x00000001 <- <- <-
0xC0F2A010 | 0x00000001 <- <- <-
0xC0F2A014 | 0x00000000 <- <- <-
0xC0F2A018 | 0x00FF02FE <- 0x01DF04FE <-
0xC0F2A01C | 0x00000000 <- <- <-
0xC0F2A020 | 0x00010001 <- <- <-
0xC0F2A024 | 0x00000000 <- <- <-
0xC0F2A028 | 0x00000000 <- <- <-
0xC0F2A02C | 0x00FF02FE <- 0x01DF04FE <-
path 'Quark' func 'Start*Path'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x02 (LVx5), 0x03 (LVx10), 0x04 (LV_VgaTele), 0x06 (LVx5), 0x07 (LVx10), 0x09 (Rec_DZ_Crop_HD), 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x0D (Rec_VgaTele), 0x0F (Rec_DZ_Crop_HD), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
Mode 0x08 ((unknown)) equals: 0x0E ((unknown)),
|
| 0x00 0x05 0x08
| LVx1 LVx1_Ta10 (unknown)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xC0F11004 | 0x00000001
0xC0F11340 | 0x00000000
0xC0F11380 | 0x00000000
0xC0F11400 | 0x00000000 <-
0xC0F11404 | 0x00000001 <-
0xC0F2A000 | 0x00000001
path 'Quark' func 'Stop*Path'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x02 (LVx5), 0x03 (LVx10), 0x04 (LV_VgaTele), 0x06 (LVx5), 0x07 (LVx10), 0x09 (Rec_DZ_Crop_HD), 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x0D (Rec_VgaTele), 0x0F (Rec_DZ_Crop_HD), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
Mode 0x08 ((unknown)) equals: 0x0E ((unknown)),
|
| 0x00 0x05 0x08
| LVx1 LVx1_Ta10 (unknown)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xC0F11004 | 0x00000000
0xC0F1100C | 0x00000000
0xC0F11340 | 0x00000001 <-
0xC0F11380 | 0x00000001 <-
0xC0F11400 | 0x00000001 <-
0xC0F11404 | 0x00000000 <-
0xC0F2A000 | 0x80000000
path 'Quark' func 'Start*YuvPass'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x02 (LVx5), 0x03 (LVx10), 0x04 (LV_VgaTele), 0x05 (LVx1_Ta10), 0x06 (LVx5), 0x07 (LVx10), 0x09 (Rec_DZ_Crop_HD), 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x0D (Rec_VgaTele), 0x0F (Rec_DZ_Crop_HD), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
Mode 0x08 ((unknown)) equals: 0x0E ((unknown)),
|
| 0x00 0x08
| LVx1 (unknown)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xC0F1100C | 0x00000001
0xC0F11340 | 0x00000000
0xC0F11380 | 0x00000000
path 'Quark' func '(unused)'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x02 (LVx5), 0x03 (LVx10), 0x04 (LV_VgaTele), 0x05 (LVx1_Ta10), 0x06 (LVx5), 0x07 (LVx10), 0x08 ((unknown)), 0x09 (Rec_DZ_Crop_HD), 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x0D (Rec_VgaTele), 0x0E ((unknown)), 0x0F (Rec_DZ_Crop_HD), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
|
| 0x00
| LVx1
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
path 'Fencing' func 'Set*Path'
Mode 0x01 (RecStandby_x1_60fps) equals: 0x11 (RecStandby_x1_60fps),
Mode 0x02 (LVx5) equals: 0x06 (LVx5),
Mode 0x03 (LVx10) equals: 0x07 (LVx10),
Mode 0x04 (LV_VgaTele) equals: 0x0D (Rec_VgaTele),
Mode 0x05 (LVx1_Ta10) equals: 0x08 ((unknown)), 0x0E ((unknown)),
Mode 0x09 (Rec_DZ_Crop_HD) equals: 0x0F (Rec_DZ_Crop_HD),
Mode 0x0A (Rec_HD) equals: 0x0C (Rec_Vga), 0x10 (RecStandby_x1), 0x12 (RecStandby_x1),
|
| 0x00 0x01 0x02 0x03 0x04 0x05 0x09 0x0A 0x0B
| LVx1 RecStandby_x1_60fps LVx5 LVx10 LV_VgaTele LVx1_Ta10 Rec_DZ_Crop_HD Rec_HD Rec_720p
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xC0F0450C | 0x00000000 <- <- <- <- <- <- <-
0xC0F04510 | 0x00FF0240 <- <- 0x027F05A0 0x01DF03C0 0x010F02D0 0x00FF0240 <-
0xC0F04514 | 0x00000000 <- <- <- <- <- <- <-
0xC0F04518 | 0x00000000 <- <- <- <- <- <- <-
0xC0F0451C | 0x00000000 <- <- <- <- <- <- <-
0xC0F04520 | 0x00000000 <- <- <- <- <- <- <-
0xC0F04524 | 0x00000000 <- <- <- <- <- <- <-
0xC0F04528 | 0x00000000 <- <- <- <- <- <- <-
0xC0F1100C | 0x00000000 <- <- <- <- <- <- <-
0xC0F11094 | 0x00000003 <- <- <- <- <- <- <-
0xC0F1110C | 0x00000003 <- <- <- <- <- <- <-
0xC0F11140 | 0x0000000A <- <- <- <- <- <- <-
0xC0F11340 | 0x00000001 <- <- <- <- <- <- <-
0xC0F11344 | 0x00011010 <- <- <- 0x00010100 0x00011010 <- <-
0xC0F11348 | 0x000530D7 0x00200823 0x0010102B 0x0006282B 0x00000000 <- 0x00200823 <-
0xC0F1134C | 0x00000000 <- <- <- <- <- <- <-
0xC0F11350 | 0x0000017F <- <- 0x000003BF 0x00000000 0x000001DF 0x0000017F <-
0xC0F11354 | 0x00FF06B8 0x00FF0690 0x00FF0408 0x027F0408 0x00000000 <- 0x00FF0690 0x01000690
0xC0F11358 | 0x00000000 <- <- <- <- <- <- <-
0xC0F1135C | 0x00000000 <- <- <- <- <- <- <-
0xC0F11380 | 0x00000001 <- <- <- <- <- <- <-
0xC0F11388 | 0x0000208F 0x00000815 0x0000102B 0x0000282B 0x00000000 <- 0x00000823 0x000040A7
0xC0F1138C | 0x00000000 <- <- <- <- <- <- <-
0xC0F11394 | 0x047706B7 0x029F068F 0x02AF0407 <- 0x00000000 <- 0x045F068F 0x029F068F
0xC0F1139C | 0x00000000 <- <- <- <- <- <- <-
0xC0F113BC | 0x00000001 <- <- <- 0x00000003 0x00000001 <- <-
0xC0F11400 | 0x00000001 <- <- <- <- <- <- <-
0xC0F11404 | 0x00000000 <- <- <- <- <- <- <-
0xC0F11408 | 0x00000000 <- <- <- <- <- <- <-
0xC0F1140C | 0x00000000 <- <- <- <- <- <- <-
0xC0F11410 | 0x00FF017F <- <- 0x027F03BF 0x01DF027F 0x010F01DF 0x00FF017F <-
0xC0F11414 | 0x00000000 <- <- <- <- <- <- <-
path 'Fencing' func 'Start*Path'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x02 (LVx5), 0x03 (LVx10), 0x04 (LV_VgaTele), 0x06 (LVx5), 0x07 (LVx10), 0x09 (Rec_DZ_Crop_HD), 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x0D (Rec_VgaTele), 0x0F (Rec_DZ_Crop_HD), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
Mode 0x05 (LVx1_Ta10) equals: 0x08 ((unknown)), 0x0E ((unknown)),
|
| 0x00 0x05
| LVx1 LVx1_Ta10
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xC0F11400 | 0x00000000
0xC0F11404 | 0x00000001
path 'Fencing' func 'Stop*Path'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x02 (LVx5), 0x03 (LVx10), 0x04 (LV_VgaTele), 0x06 (LVx5), 0x07 (LVx10), 0x09 (Rec_DZ_Crop_HD), 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x0D (Rec_VgaTele), 0x0F (Rec_DZ_Crop_HD), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
Mode 0x05 (LVx1_Ta10) equals: 0x08 ((unknown)), 0x0E ((unknown)),
|
| 0x00 0x05
| LVx1 LVx1_Ta10
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xC0F1100C | 0x00000000
0xC0F11340 | 0x00000001
0xC0F11380 | 0x00000001
0xC0F11400 | 0x00000001
0xC0F11404 | 0x00000000
path 'Fencing' func 'Start*YuvPass'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x02 (LVx5), 0x03 (LVx10), 0x04 (LV_VgaTele), 0x06 (LVx5), 0x07 (LVx10), 0x09 (Rec_DZ_Crop_HD), 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x0D (Rec_VgaTele), 0x0F (Rec_DZ_Crop_HD), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
Mode 0x05 (LVx1_Ta10) equals: 0x08 ((unknown)), 0x0E ((unknown)),
|
| 0x00 0x05
| LVx1 LVx1_Ta10
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xC0F1100C | 0x00000001
0xC0F11340 | 0x00000000
0xC0F11380 | 0x00000000
path 'Fencing' func '(unused)'
Mode 0x00 (LVx1) equals: 0x01 (RecStandby_x1_60fps), 0x02 (LVx5), 0x03 (LVx10), 0x04 (LV_VgaTele), 0x05 (LVx1_Ta10), 0x06 (LVx5), 0x07 (LVx10), 0x08 ((unknown)), 0x09 (Rec_DZ_Crop_HD), 0x0A (Rec_HD), 0x0B (Rec_720p), 0x0C (Rec_Vga), 0x0D (Rec_VgaTele), 0x0E ((unknown)), 0x0F (Rec_DZ_Crop_HD), 0x10 (RecStandby_x1), 0x11 (RecStandby_x1_60fps), 0x12 (RecStandby_x1),
|
| 0x00
| LVx1
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
sht_mirror[]
C0F01000 ... C0F01040: POWER CONTROL C0F03000 ... C0F030C8: SHAREMEM1 C0F03200 ... C0F03350: SHAREMEM2 C0F04000 ... C0F04050: DMAC CONTROL WR0 C0F04100 ... C0F04150: DMAC CONTROL WR1 C0F04200 ... C0F04250: DMAC CONTROL WR2 C0F04300 ... C0F04350: DMAC CONTROL WR3 C0F04400 ... C0F04450: DMAC CONTROL WR4 C0F04500 ... C0F04550: DMAC CONTROL WR5 C0F04600 ... C0F04650: DMAC CONTROL WR6 C0F26000 ... C0F26050: DMAC CONTROL WR7 C0F26100 ... C0F26150: DMAC CONTROL WR8 C0F26200 ... C0F26250: DMAC CONTROL WR9 C0F04800 ... C0F04850: DMAC CONTROL RD0 C0F04900 ... C0F04950: DMAC CONTROL RD1 C0F04A00 ... C0F04A50: DMAC CONTROL RD2 C0F04B00 ... C0F04B50: DMAC CONTROL RD3 C0F04C00 ... C0F04C50: DMAC CONTROL RD4 C0F04D00 ... C0F04D50: DMAC CONTROL RD5 C0F26800 ... C0F26850: DMAC CONTROL RD6 C0F26900 ... C0F26950: DMAC CONTROL RD7 C0F05000 ... C0F050AC: DMAC CH SWITCH C0F07000 ... C0F072B0: HEAD CONTROL C0F11000 ... C0F11170: RESAMPLE SEL C0F11500 ... C0F1152C: RESAMPLE LESSER H C0F11540 ... C0F1156C: RESAMPLE LESSER V C0F13000 ... C0F13068: RABBIT C0F0D000 ... C0F0D0AC: SNDPAS C0F2C000 ... C0F2C034: JUKAI C0F09000 ... C0F090A4: FSTPAS C0F0E000 ... C0F0E184: OBINTEG C0F0B000 ... C0F0B104: WBTHM C0F38000 ... C0F38C4C: SHREK
See DMA http://magiclantern.wikia.com/wiki/DMA
See DIGIC